mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-04 22:32:36 +00:00
maksyuki
3cf9e4c6a6
- Modified dma_core to accommodate a wider data width for FIFO operations. - Updated filelists to include new DVP source files and formal verification files. - Introduced formal verification modules for DVP functionality. - Enhanced clock and reset domain configurations for DVP integration. - Added DVP interrupt handling in the IRQ topology. - Implemented a testbench for DVP to validate register access and frame processing. - Updated software build scripts to include DVP-related source files. - Adjusted the system topology to reflect the new DVP interrupt and IRQ mapping.
300 lines
9.6 KiB
Systemverilog
300 lines
9.6 KiB
Systemverilog
// Copyright (c) 2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
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// retroSoC is licensed under Mulan PSL v2.
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`include "dvp_define.svh"
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/* verilator lint_off DECLFILENAME */
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interface dvp_if ();
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logic pclk_i;
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logic href_i;
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logic vsync_i;
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logic [7:0] dat_i;
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modport dut(input pclk_i, input href_i, input vsync_i, input dat_i);
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endinterface
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/* verilator lint_on DECLFILENAME */
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module ribp_dvp (
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// verilog_format: off
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input logic clk_i,
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input logic rst_n_i,
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ribp_if.slave ribp,
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axi4_stream_if.source rx_axis,
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dvp_if.dut dvp,
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output logic irq_o
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// verilog_format: on
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);
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localparam int DVP_PAYLOAD_WIDTH = 42;
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logic [ 127:0] s_config_sys;
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logic s_cfg_v_sys;
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logic s_cfg_rdy_sys;
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logic [ 127:0] s_cfg_pclk_q;
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logic s_cfg_v_pclk;
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logic s_cfg_rdy_pclk;
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logic [ 1:0] s_cmd_sys;
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logic [ 1:0] s_cmd_pclk;
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logic s_cmd_v_pclk;
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logic s_cmd_rdy_pclk;
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logic s_cmd_rdy_sys;
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logic s_cmd_v_sys;
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logic [ 1:0] s_cmd_core;
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logic s_cmd_abort_sys;
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logic s_cmd_flush_sys;
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logic s_pclk_inv;
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logic s_pclk_buf;
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logic s_pclk_rst_n;
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logic s_pclk_sel;
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logic s_pclk_falling;
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logic s_active;
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logic s_stream_en;
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logic s_fifo_src_ready;
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logic s_fifo_dst_valid;
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logic [DVP_PAYLOAD_WIDTH-1:0] s_fifo_dst_data;
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logic s_fifo_dst_ready;
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logic s_fifo_src_clear;
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logic s_fifo_src_clear_busy;
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logic s_fifo_dst_clear_busy;
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logic [ 31:0] s_fifo_rx_data;
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logic s_rx_pop;
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logic s_fifo_full_sys;
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logic s_fifo_empty_sys;
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logic s_frm_start_tgl;
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logic s_line_done_tgl;
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logic s_frm_done_tgl;
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logic s_err_tgl;
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logic s_frame_start_event;
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logic s_line_done_event;
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logic s_frame_done_event;
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logic s_err_evt;
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logic [ 5:0] s_err_flags_pclk;
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logic [ 5:0] s_err_flags_sys;
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logic [ 127:0] s_frm_stats_pclk;
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logic s_frm_stats_v_pclk;
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logic s_frm_stats_rdy_pclk;
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logic [ 127:0] s_frm_stats_sys;
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logic s_frm_stats_v_sys;
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assign s_cmd_sys = {s_cmd_flush_sys, s_cmd_abort_sys};
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// Commands are consumed in the pixel domain as soon as they cross the CDC.
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assign s_cmd_rdy_pclk = !s_fifo_src_clear_busy;
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assign s_pclk_falling = s_config_sys[106];
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assign s_fifo_src_clear = s_cmd_pclk[`DVP_COMMAND_FLUSH] || s_cmd_pclk[`DVP_COMMAND_ABORT];
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assign s_fifo_dst_ready = !s_fifo_dst_clear_busy && (s_stream_en ? rx_axis.tready : s_rx_pop);
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assign s_fifo_rx_data = s_fifo_dst_data[31:0];
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assign s_fifo_empty_sys = !s_fifo_dst_valid;
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tc_clk_buf u_dvp_pclk_clk_buf (
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.clk_i(dvp.pclk_i),
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.clk_o(s_pclk_buf)
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);
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tc_clk_inv u_dvp_pclk_inv (
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.clk_i(s_pclk_buf),
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.clk_o(s_pclk_inv)
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);
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tc_clk_mux2 u_dvp_pclk_mux (
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.clk0_i (s_pclk_buf),
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.clk1_i (s_pclk_inv),
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.clk_sel_i(s_pclk_falling),
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.clk_o (s_pclk_sel)
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);
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rst_sync #(
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.STAGE(5)
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) u_dvp_pclk_rst_sync (
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.clk_i (s_pclk_sel),
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.rst_n_i(rst_n_i),
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.rst_n_o(s_pclk_rst_n)
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);
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dvp_reg u_dvp_reg (
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.clk_i (clk_i),
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.rst_n_i (rst_n_i),
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.ribp (ribp),
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.active_i (s_active),
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.fifo_empty_i (s_fifo_empty_sys),
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.fifo_full_i (s_fifo_full_sys),
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.rx_data_i (s_fifo_rx_data),
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.frame_start_i (s_frame_start_event),
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.line_done_i (s_line_done_event),
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.frame_done_i (s_frame_done_event),
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.error_event_i (s_err_evt),
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.error_flags_i (s_err_flags_sys),
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.frame_stats_i (s_frm_stats_sys),
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.frame_stats_valid_i(s_frm_stats_v_sys),
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.config_o (s_config_sys),
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.config_valid_o (s_cfg_v_sys),
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.config_ready_i (s_cfg_rdy_sys),
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.command_abort_o (s_cmd_abort_sys),
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.command_flush_o (s_cmd_flush_sys),
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.command_valid_o (s_cmd_v_sys),
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.command_ready_i (s_cmd_rdy_sys),
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.rx_pop_o (s_rx_pop),
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.stream_enable_o (s_stream_en),
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.irq_o (irq_o)
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);
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cdc_2phase #(
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.DATA_WIDTH(128)
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) u_dvp_config_cdc (
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.src_clk_i (clk_i),
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.src_rst_n_i(rst_n_i),
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.src_data_i (s_config_sys),
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.src_valid_i(s_cfg_v_sys),
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.src_ready_o(s_cfg_rdy_sys),
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.dst_clk_i (s_pclk_sel),
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.dst_rst_n_i(s_pclk_rst_n),
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.dst_data_o (s_cfg_pclk_q),
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.dst_valid_o(s_cfg_v_pclk),
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.dst_ready_i(s_cfg_rdy_pclk)
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);
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cdc_2phase #(
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.DATA_WIDTH(2)
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) u_dvp_command_cdc (
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.src_clk_i (clk_i),
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.src_rst_n_i(rst_n_i),
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.src_data_i (s_cmd_sys),
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.src_valid_i(s_cmd_v_sys),
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.src_ready_o(s_cmd_rdy_sys),
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.dst_clk_i (s_pclk_sel),
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.dst_rst_n_i(s_pclk_rst_n),
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.dst_data_o (s_cmd_pclk),
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.dst_valid_o(s_cmd_v_pclk),
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.dst_ready_i(s_cmd_rdy_pclk)
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);
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cdc_fifo_warm_flush #(
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.DATA_WIDTH (DVP_PAYLOAD_WIDTH),
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.BUFFER_DEPTH(128)
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) u_dvp_payload_fifo (
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.src_clk_i (s_pclk_sel),
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.src_rst_n_i (s_pclk_rst_n),
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.src_clear_i (s_fifo_src_clear),
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.src_clear_busy_o(s_fifo_src_clear_busy),
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.src_data_i (s_core_push_data),
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.src_valid_i (s_core_push_valid),
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.src_ready_o (s_fifo_src_ready),
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.dst_clk_i (clk_i),
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.dst_rst_n_i (rst_n_i),
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.dst_clear_busy_o(s_fifo_dst_clear_busy),
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.dst_data_o (s_fifo_dst_data),
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.dst_valid_o (s_fifo_dst_valid),
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.dst_ready_i (s_fifo_dst_ready)
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);
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logic [DVP_PAYLOAD_WIDTH-1:0] s_core_push_data;
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logic s_core_push_valid;
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assign s_cmd_core = s_cmd_v_pclk ? s_cmd_pclk : 2'b00;
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cdc_sync #(
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.STAGE (2),
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.DATA_WIDTH(1)
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) u_fifo_full_sync (
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.clk_i (clk_i),
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.rst_n_i(rst_n_i),
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.dat_i (!s_fifo_src_ready),
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.dat_o (s_fifo_full_sys)
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);
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cdc_sync #(
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.STAGE (2),
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.DATA_WIDTH(6)
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) u_error_flags_sync (
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.clk_i (clk_i),
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.rst_n_i(rst_n_i),
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.dat_i (s_err_flags_pclk),
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.dat_o (s_err_flags_sys)
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);
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/* verilator lint_off PINCONNECTEMPTY */
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edge_det #(
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.STAGE(2)
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) u_frame_start_event (
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.clk_i (clk_i),
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.rst_n_i(rst_n_i),
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.dat_i (s_frm_start_tgl),
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.dat_o (),
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.re_o (s_frame_start_event),
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.fe_o ()
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);
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edge_det #(
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.STAGE(2)
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) u_line_done_event (
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.clk_i (clk_i),
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.rst_n_i(rst_n_i),
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.dat_i (s_line_done_tgl),
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.dat_o (),
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.re_o (s_line_done_event),
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.fe_o ()
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);
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edge_det #(
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.STAGE(2)
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) u_frame_done_event (
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.clk_i (clk_i),
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.rst_n_i(rst_n_i),
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.dat_i (s_frm_done_tgl),
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.dat_o (),
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.re_o (s_frame_done_event),
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.fe_o ()
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);
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edge_det #(
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.STAGE(2)
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) u_error_event (
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.clk_i (clk_i),
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.rst_n_i(rst_n_i),
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.dat_i (s_err_tgl),
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.dat_o (),
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.re_o (s_err_evt),
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.fe_o ()
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);
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/* verilator lint_on PINCONNECTEMPTY */
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cdc_2phase #(
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.DATA_WIDTH(128)
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) u_dvp_stats_cdc (
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.src_clk_i (s_pclk_sel),
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.src_rst_n_i(s_pclk_rst_n),
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.src_data_i (s_frm_stats_pclk),
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.src_valid_i(s_frm_stats_v_pclk),
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.src_ready_o(s_frm_stats_rdy_pclk),
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.dst_clk_i (clk_i),
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.dst_rst_n_i(rst_n_i),
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.dst_data_o (s_frm_stats_sys),
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.dst_valid_o(s_frm_stats_v_sys),
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.dst_ready_i(1'b1)
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);
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assign rx_axis.tdata = s_fifo_dst_data[31:0];
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assign rx_axis.tkeep = s_fifo_dst_data[39:36];
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assign rx_axis.tstrb = s_fifo_dst_data[35:32];
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assign rx_axis.tlast = s_fifo_dst_data[40];
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assign rx_axis.tid = '0;
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assign rx_axis.tdest = '0;
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assign rx_axis.tuser = s_fifo_dst_data[41];
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assign rx_axis.tvalid = s_stream_en && s_fifo_dst_valid;
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dvp_core u_dvp_core (
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.clk_i (s_pclk_sel),
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.rst_n_i (s_pclk_rst_n),
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.config_i (s_cfg_pclk_q),
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.config_valid_i (s_cfg_v_pclk),
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.command_i (s_cmd_core),
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.config_ready_o (s_cfg_rdy_pclk),
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.push_ready_i (s_fifo_src_ready),
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.push_valid_o (s_core_push_valid),
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.push_data_o (s_core_push_data),
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.active_o (s_active),
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.frame_start_toggle_o(s_frm_start_tgl),
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.line_done_toggle_o (s_line_done_tgl),
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.frame_done_toggle_o (s_frm_done_tgl),
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.error_toggle_o (s_err_tgl),
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.error_flags_o (s_err_flags_pclk),
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.frame_stats_o (s_frm_stats_pclk),
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.frame_stats_valid_o (s_frm_stats_v_pclk),
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.frame_stats_ready_i (s_frm_stats_rdy_pclk),
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.href_i (dvp.href_i),
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.vsync_i (dvp.vsync_i),
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.dat_i (dvp.dat_i)
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);
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endmodule
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