mirror of
https://github.com/retroSoC/retroSoC.git
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maksyuki
b5cbc89928
- Implemented a new TCL script for Tiny R2 feasibility checks, reporting clock properties, path delays, and reset loads. - Created a SystemVerilog module for the Tiny R2 reset tree, managing multiple reset signals for the system and its leaves. - Developed a Python script for capturing and analyzing feasibility metrics, ensuring compliance with reset-load and clock frequency requirements. - Added testbenches for the Tiny R2 reset tree and FIFO, validating reset behavior and timing contracts. - Introduced unit tests for feasibility analysis, ensuring correct handling of clock rates and reset load conditions.
46 lines
1.4 KiB
Python
46 lines
1.4 KiB
Python
"""Directed reset-sequencing test for the management Hazard3 debug path."""
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from __future__ import annotations
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import shutil
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import subprocess
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from pathlib import Path
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import pytest
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ROOT = Path(__file__).resolve().parents[1]
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@pytest.mark.parametrize("stages", [3, 5])
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def test_management_debug_reset_waits_for_the_ahbl_bridge(tmp_path: Path, stages: int) -> None:
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iverilog = shutil.which("iverilog")
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vvp = shutil.which("vvp")
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if iverilog is None or vvp is None:
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return
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simulation = tmp_path / "mgmt_debug_reset_tb"
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sources = (
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ROOT / "rtl/managed/clusterip/common/rtl/utils/register.sv",
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ROOT / "rtl/managed/clusterip/common/rtl/clkrst/rst_sync.sv",
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ROOT / "rtl/ip/core/mgmt_debug_reset.sv",
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ROOT / "tests/rtl/mgmt_debug_reset_tb.sv",
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)
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subprocess.run(
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[
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iverilog,
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"-g2012",
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"-DSV_ASSRT_DISABLE",
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f"-I{ROOT / 'rtl/managed/clusterip/common/rtl'}",
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"-s",
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"mgmt_debug_reset_tb",
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f"-Pmgmt_debug_reset_tb.ResetSyncStages={stages}",
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"-o",
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str(simulation),
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*(str(source) for source in sources),
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],
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check=True,
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)
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result = subprocess.run([vvp, str(simulation)], text=True, capture_output=True, check=True)
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assert "management debug reset test passed" in result.stdout
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