mirror of
https://github.com/retroSoC/retroSoC.git
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55 lines
1.8 KiB
YAML
55 lines
1.8 KiB
YAML
name: test
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on:
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push:
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branches: [ main, dev ]
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pull_request:
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branches: [ main, dev ]
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jobs:
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build:
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runs-on: ubuntu-22.04
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steps:
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- name: Checkout Repository
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uses: actions/checkout@v4
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- name: Download and extract RISC-V toolchain
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run: |
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wget https://github.com/riscv-collab/riscv-gnu-toolchain/releases/download/2021.09.21/riscv32-elf-ubuntu-20.04-nightly-2021.09.21-nightly.tar.gz
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tar -xzf riscv32-elf-ubuntu-20.04-nightly-2021.09.21-nightly.tar.gz -C /tmp
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toolchain_bin="/tmp/riscv32-elf-ubuntu-20.04-nightly-2021.09.21-nightly/bin"
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echo "RISCV_TOOLCHAIN_BIN=$toolchain_bin" >> $GITHUB_ENV
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echo "$toolchain_bin" >> $GITHUB_PATH
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- name: Use the toolchain in a subsequent step
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run: |
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echo "The toolchain path is $RISCV_TOOLCHAIN_BIN"
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riscv32-unknown-elf-gcc --version
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- name: Setup Environment
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run: python3 setup.py
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- name: Compile Firmware
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run: make CORE=MDD IP=MDD SIMU=VERILATOR HAVE_SRAM_IF=NO HAVE_SRAM_MACRO=NO HAVE_PLL=NO ISA=RV32IM EXEC_TYPE=ld2_psram firmware
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- name: Build and Run sim
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run: make CORE=MDD IP=MDD SIMU=VERILATOR HAVE_SRAM_IF=NO HAVE_SRAM_MACRO=NO HAVE_PLL=NO ISA=RV32IM EXEC_TYPE=ld2_psram sim
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- name: Success Notification
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run: echo "Workflow completed successfully"
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# jobs:
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# lint-tgt:
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# name: SystemVerilog Lint
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# runs-on: ubuntu-latest
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# steps:
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# - uses: actions/checkout@v3
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# - uses: chipsalliance/verible-linter-action@main
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# with:
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# paths: |
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# ./rtl
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# # extra_args: "--waiver_files lint/common_cells.style.waiver --rules=-interface-name-style --lint_fatal"
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# # github_token: ${{ secrets.GITHUB_TOKEN }}
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# # reviewdog_reporter: github-check
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