mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-04 22:32:36 +00:00
105 lines
3.4 KiB
Makefile
105 lines
3.4 KiB
Makefile
SOC ?= MINI
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SIMU ?= VCS
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SYNTH ?= YOSYS
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TIMI ?= OPENSTA
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# HW
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PDK ?= IHP130
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HAVE_PLL ?= YES
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HAVE_SRAM_IF ?= YES
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HAVE_SRAM_MACRO ?= YES
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HAVE_SVA ?= NO
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RTL_SIM_PLLEN ?= NONE
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RTL_SIM_PLLCFG ?= NONE
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RTL_SIM_CORESEL ?= 0
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WAVE ?= NONE
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ROOT_PATH ?= $(CURDIR)
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RTL_PATH ?= NONE
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CORE ?= PICORV32
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IP ?= NONE
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RTL_TOP ?= retrosoc_tb
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# SW
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ISA ?= RV32IM
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FIRMWARE_NAME ?= retrosoc_fw
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EXEC_TYPE ?= ld2_sram
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$(info ============== BASE INFO ==================================)
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$(info retroSoC: <https://github.com/retroSoC/retroSoC>)
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$(info author: Yuchi Miao <https://github.com/maksyuki>)
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$(info license: MulanPSL-2.0 license)
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$(info ROOT_PATH: $(CURDIR))
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$(info SHELL: $(SHELL))
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$(info MAKE VERSION: $(MAKE_VERSION))
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$(info MAKE APP: $(MAKE))
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$(info MAKE CMDGOAL: $(MAKECMDGOALS))
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$(info MAKE FILELIST: $(MAKEFILE_LIST))
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$(info ============== HW CONFIG INFO =============================)
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$(info SOC [TINY, MINI]: $(SOC))
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$(info CORE [PICORV32, MDD]: $(CORE))
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$(info IP [NONE, MDD]: $(IP))
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$(info SIMU [VCS, VERILATOR]: $(SIMU))
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$(info SYNTH [YOSYS, DC]: $(SYNTH))
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$(info TIMI [OPENSTA, ISTA]: $(TIMI))
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$(info PDK [S110, IHP130, SKY130, ICS55]: $(PDK))
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$(info HAVE_PLL [YES, NO]: $(HAVE_PLL))
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$(info HAVE_SRAM_IF [YES, NO]: $(HAVE_SRAM_IF))
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$(info HAVE_SRAM_MACRO [YES, NO]: $(HAVE_SRAM_MACRO))
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$(info HAVE_SVA [YES, NO]: $(HAVE_SVA))
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$(info RTL_SIM_PLLEN: $(RTL_SIM_PLLEN))
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$(info RTL_SIM_PLLCFG: $(RTL_SIM_PLLCFG))
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$(info RTL_SIM_CORESEL: $(RTL_SIM_CORESEL))
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$(info WAVE: $(WAVE))
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$(info ============== SW CONFIG INFO =============================)
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$(info ISA [RV32E RV32I RV32IM]: $(ISA))
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$(info FIRMWARE_NAME [retrosoc_fw]: $(FIRMWARE_NAME))
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$(info EXEC_TYPE [xip ld2_sram ld2_psram]: $(EXEC_TYPE))
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$(info ===========================================================)
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DEF_LIST ?= +define+PDK_$(PDK)
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DEF_LIST += +define+CORE_$(CORE)
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DEF_LIST += +define+IP_$(IP)
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DEF_LIST += +define+SIMU_$(SIMU)
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ifeq ($(HAVE_PLL), YES)
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DEF_LIST += +define+HAVE_PLL
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endif
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ifeq ($(HAVE_SRAM_IF), YES)
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DEF_LIST += +define+HAVE_SRAM_IF
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endif
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ifeq ($(HAVE_SRAM_MACRO), YES)
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DEF_LIST += +define+HAVE_SRAM_MACRO
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endif
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ifeq ($(HAVE_SVA), NO)
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DEF_LIST += +define+SV_ASSRT_DISABLE
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endif
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ifeq ($(SOC), MINI)
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RTL_PATH = $(ROOT_PATH)/rtl/mini
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$(info DEF_LIST: $(DEF_LIST))
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$(file > $(RTL_PATH)/filelist/def.fl, $(DEF_LIST))
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include rtl/mini/Makefile
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endif
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ifeq ($(SOC), TINY)
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RTL_PATH = $(ROOT_PATH)/rtl/tiny
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$(info DEF_LIST: $(DEF_LIST))
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$(file > $(RTL_PATH)/filelist/def.fl, $(DEF_LIST))
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include rtl/tiny/Makefile
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endif
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ifeq ($(SYNTH), YOSYS)
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DEF_LIST += +define+SYNTHESIS #HACK: for some core
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$(info SYNTH DEF_LIST: $(DEF_LIST))
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$(file > $(RTL_PATH)/filelist/def.fl, $(DEF_LIST))
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demo := $(shell python3 $(RTL_PATH)/filelist/comb.py $(RTL_FLIST))
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include syn/yosys/yosys.mk
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else ifeq ($(SYNTH), DC)
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include syn/dc.mk
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endif |