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maksyuki
a64526c6a9
Implement SPI-P1 from docs/ip/spi.md with a PCLK master, registered APB responses, packed 8x32 TX/RX FIFOs, finite quotas and retained-session abort/recovery. Add the handwritten SVH/C register mirror and private source, credit and GPIO qualification interfaces. Add independent pin timing and data checks, malformed-waveform negatives, FIFO stall/resume and phase-safe abort cases. Provide isolated lint, simulation, compositional formal, synthesis, netlist and observational STA flows with source-bound artifacts and tool-component fingerprints. Validation on the reviewed worktree: 2085 pytest tests passed and one optional pypdf test skipped; both RTL simulators, fresh depth-192 BMC and cover, and ICS55/IHP130 block synthesis and netlist simulation passed. Formatting, style/readiness, Ruff and regression dry-runs passed. SPI remains outside product filelists with DMA capability disabled. SPI-P2/P3 integration, full-product regression closure and physical/IO qualification remain pending; no phase acceptance or policy change.
Physical Design
This directory owns physical-design integration, managed technology inputs, smoke implementation-flow sources, and the self-developed commercial-flow drivers.
pdk/contains the locked PDK setup helpers and managed PDK checkouts.smoke/syn/contains Yosys synthesis and source-export integration.smoke/sta/contains OpenSTA constraints and timing integration.librelane/contains the open-source IHP130 implementation flows, organized per product line:librelane/mini/(core hardening and full-chip pad ring) andlibrelane/tiny/(Tiny full-chip pad ring).ecc/contains the ICS55 padless-core adapter and the official ECClatestinstaller entrypoint. Installation does not qualify physical-flow compatibility.commercial/contains licensed-tool orchestration and flow logic for the ICS55 implementation flow, parameterized per product line (SOC=MINIandSOC=TINY, extensible to future series). PDKs, foundry decks, commercial libraries, site configuration, and results remain outside Git; see commercial/README.md for the three-layer configuration model and stage graph.sdf/, when supplied by an implementation flow, contains post-layout netlist and SDF collateral consumed by post-layout simulation.
The local Makefile is reserved for implementation flows that require the selected PDK, technology collateral, and often site-specific tools.
Generated layout, report, and database outputs must remain outside tracked source paths. Treat PDK-dependent physical-design results as toolchain-specific evidence and record the selected profile, PDK, and validation command when handing off a change. See Engineering Workflow.