maksyuki
4b3553faa7
Document the standalone interfaces, timing checker, FIFO pressure cases, tool-component identity and exact execution commands. Update subsystem guides and the verification ledger with the matching ICS55/IHP130 evidence. Keep historical failures and producer identities separate from the new results. Record the optional PDF-test skip, unconstrained IO boundaries, deferred full-product regressions and the human phase-acceptance gate. Validation: 21 local links and the documentation-only post-test delta checked; git diff --check passed. No generated evidence is committed.
2.2 KiB
Shared RTL IP
This directory owns project RTL IP.
Self-owned IP is grouped by function: interconnect, util, memory, storage,
serial, USB, multimedia, and peripheral. Mini and Tiny select active sources
explicitly in their product filelists.
Source order is part of the build contract. Shared Hazard3/debug wrappers are
in core, AXI adapters in interconnect, and native AXI SRAM in memory.
Both products reference these shared files directly in their own filelists.
Tiny does not select any RIB/RIBP module.
The PIO-lite contract specifies a future owned programmable-I/O block for Tiny, with shared GPIO ownership and DMA V2.1 integration changes. Its planned hierarchy is not present in the active filelists yet. The verification ledger keeps model, RTL, integration and physical gates separate from design freeze; shared DMA/GPIO changes must preserve Mini behavior without enabling PIO there.
The independent SPI master is a separately frozen future
Tiny block, distinct from SPI-SD and XPI. Its APB/packed FIFOs, native GPIO
guard, source-qualified DMA V2.2 MMIO pacing and SPI-P0..P5 gates are defined
there, with pending verification. A
specification or reserved route does not add it to the current RTL/filelists.
The SPI-P1 standalone implementation is isolated
from product filelists. Its DMA capability remains clear; actual DMA V2.2,
Tiny routing, lifecycle and SDK integration belong to P2/P3.
The PPALite contract specifies a future camera-inline PCLK processor with RAW bypass, small FIFOs and existing DVP_RX11/DMA2 output. Its verification ledger makes DVP source error/statistic/CDC and drain qualification prerequisites explicit. Shared correctness work preserves the DVP V2 ABI/FIFO and Mini RAW behavior; it does not import GA2D's private DMA or enable a new master or product rollout.
experimental contains retained inactive RTL. It is not included by any active filelist and must not become a build dependency without an explicit integration change and matching validation.