mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-04 22:32:36 +00:00
maksyuki
4b40dbf262
- Updated the formal file list generator to include CLINT source files. - Added CLINT timebase to the clock and reset domains configuration. - Enhanced the SOC topology generation to include CLINT interrupts and their mappings. - Introduced a new CLINT testbench to validate multi-hart and timebase functionality. - Modified the software build configuration to define CLINT timebase frequency. - Updated the RCU module to integrate CLINT timebase generation. - Adjusted the IRQ configuration to reflect changes in CLINT interrupt signals. - Added user-visible flags for interrupts in the topology configuration. - Enhanced the clock reset domain checks to include CLINT timebase. - Updated the memory map tests to validate CLINT peripheral integration.
16 lines
323 B
Systemverilog
16 lines
323 B
Systemverilog
// Copyright (c) 2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
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// retroSoC is licensed under Mulan PSL v2.
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`ifndef RETROSOC_SOC_CLOCK_CONFIG_SVH
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`define RETROSOC_SOC_CLOCK_CONFIG_SVH
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`ifndef SOC_EXT_CLK_HZ
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`define SOC_EXT_CLK_HZ 72000000
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`endif
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`ifndef SOC_CLINT_TIMEBASE_HZ
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`define SOC_CLINT_TIMEBASE_HZ 1000000
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`endif
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`endif
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