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110 lines
3.5 KiB
Systemverilog
110 lines
3.5 KiB
Systemverilog
// Copyright (c) 2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
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// retroSoC is licensed under Mulan PSL v2.
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module uart_formal_design (
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// verilog_format: off
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input logic clk_i,
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output logic rst_n_i,
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output logic f_past_valid,
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output logic rib_valid,
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output logic [31:0] rib_addr,
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output logic [31:0] rib_wdata,
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output logic [ 3:0] rib_wstrb,
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output logic rib_ready,
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output logic rib_resp_err,
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output logic [ 6:0] tx_count,
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output logic [ 6:0] rx_count,
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output logic [ 6:0] error_status,
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output logic [ 6:0] intr_state,
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output logic [ 6:0] intr_enable,
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output logic tx_enable,
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output logic rx_enable,
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output logic tx_busy,
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output logic rx_active,
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output logic break_active,
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output logic auto_cts_enable,
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output logic auto_rts_enable,
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output logic cts_asserted,
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output logic rts_asserted,
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output logic tx_start_allowed,
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output logic tx_flow_blocked,
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output logic tx_data_pop,
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output logic tx_dma_stall,
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output logic rx_dma_stall,
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output logic tx,
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output logic rts_n,
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output logic irq
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// verilog_format: on
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);
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apb4_if apb4 (
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.pclk (clk_i),
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.presetn(rst_n_i)
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);
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uart_if uart ();
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(* anyseq *)logic f_apb_sel;
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(* anyseq *)logic [31:0] f_apb_addr;
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(* anyseq *)logic [31:0] f_apb_wdata;
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(* anyseq *)logic [ 3:0] f_apb_pstrb;
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(* anyseq *)logic f_uart_rx;
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(* anyseq *)logic f_uart_cts_n;
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assign apb4.psel = f_apb_sel;
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assign apb4.penable = f_apb_sel;
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assign apb4.pwrite = |f_apb_pstrb;
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assign apb4.paddr = f_apb_addr;
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assign apb4.pwdata = f_apb_wdata;
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assign apb4.pstrb = f_apb_pstrb;
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assign apb4.pprot = 3'b000;
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assign uart.rx_i = f_uart_rx;
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assign uart.cts_n_i = f_uart_cts_n;
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assign rib_valid = apb4.psel;
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assign rib_addr = apb4.paddr;
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assign rib_wdata = apb4.pwdata;
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assign rib_wstrb = apb4.pstrb;
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assign rib_ready = apb4.pready;
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assign rib_resp_err = apb4.pslverr;
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assign tx_count = u_dut.u_uart_reg.s_tx_count;
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assign rx_count = u_dut.u_uart_reg.s_rx_count;
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assign error_status = u_dut.u_uart_reg.s_err_stat_q;
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assign intr_state = u_dut.u_uart_reg.s_intr_state_q;
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assign intr_enable = u_dut.u_uart_reg.s_intr_en_q;
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assign tx_enable = u_dut.s_tx_en;
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assign rx_enable = u_dut.s_rx_en;
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assign tx_busy = u_dut.s_tx_busy;
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assign rx_active = u_dut.s_rx_active;
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assign break_active = u_dut.s_break;
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assign auto_cts_enable = u_dut.s_auto_cts_en;
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assign auto_rts_enable = u_dut.s_auto_rts_en;
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assign cts_asserted = u_dut.s_cts_asserted;
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assign rts_asserted = u_dut.s_rts_asserted;
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assign tx_start_allowed = u_dut.s_tx_start_allowed;
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assign tx_flow_blocked = u_dut.s_tx_flow_blocked;
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assign tx_data_pop = u_dut.s_tx_data_pop;
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assign tx = uart.tx_o;
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assign rts_n = uart.rts_n_o;
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assign irq = uart.irq_o;
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apb4_uart u_dut (
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.clk_i (clk_i),
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.rst_n_i (rst_n_i),
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.dma_tx_stall_o(tx_dma_stall),
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.dma_rx_stall_o(rx_dma_stall),
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.apb4 (apb4),
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.uart (uart)
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);
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initial begin
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rst_n_i = 1'b0;
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f_past_valid = 1'b0;
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end
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always_ff @(posedge clk_i) begin
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rst_n_i <= 1'b1;
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f_past_valid <= 1'b1;
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end
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endmodule
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