mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-06 14:55:14 +00:00
maksyuki
1eb342245c
- Replace onewire interface with ws2812 interface in retrosoc module. - Include ws2812_math.c in C test sources. - Add ws2812 header in test_runtime.c and implement ws2812 helper tests. - Update ribp_topology_tb and soc_irq_topology_tb to handle ws2812 interface. - Create ws2812_dma_tb and ws2812_tb for testing WS2812 DMA and waveform functionality. - Enhance test_script_tools.py to include ws2812 in formal filelists. - Modify test_soc_topology.py to ensure proper IRQ mapping for ws2812. - Introduce test_ws2812.py for WS2812 register, waveform, and streaming regression tests.
133 lines
4.3 KiB
Python
133 lines
4.3 KiB
Python
"""WS2812 register, waveform, and streaming regression tests."""
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from __future__ import annotations
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import shutil
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import subprocess
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import sys
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from pathlib import Path
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ROOT = Path(__file__).resolve().parents[1]
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def test_ws2812_register_waveform_streaming_and_errors(tmp_path: Path) -> None:
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iverilog = shutil.which("iverilog")
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vvp = shutil.which("vvp")
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if iverilog is None or vvp is None:
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return
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common = ROOT / "rtl/managed/clusterip/common/rtl"
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serial = ROOT / "rtl/ip/ribp/serial"
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source_list = tmp_path / "ws2812.fl"
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source_list.write_text(
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"\n".join(
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[
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"+define+SV_ASSRT_DISABLE",
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f"+incdir+{common}",
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f"+incdir+{common / 'interface'}",
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f"+incdir+{common / 'utils'}",
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f"+incdir+{serial}",
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str(common / "interface/ribp_if.sv"),
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str(common / "utils/register.sv"),
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str(common / "utils/fifo.sv"),
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str(serial / "ws2812_if.sv"),
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str(serial / "ws2812_reg.sv"),
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str(serial / "ws2812_core.sv"),
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str(serial / "ribp_ws2812.sv"),
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str(ROOT / "tests/rtl/ws2812_tb.sv"),
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"",
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]
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),
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encoding="utf-8",
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)
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converted = tmp_path / "ws2812_tb.v"
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subprocess.run(
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[
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sys.executable,
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str(ROOT / "rtl/mini/script/convt_sv2v.py"),
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"-f",
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str(source_list),
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"--output",
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str(converted),
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],
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check=True,
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)
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simulation = tmp_path / "ws2812_tb"
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subprocess.run(
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[iverilog, "-g2012", "-s", "ws2812_tb", "-o", str(simulation), str(converted)],
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check=True,
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)
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result = subprocess.run([vvp, str(simulation)], text=True, capture_output=True, check=True)
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assert "WS2812 register, waveform, streaming, and error test passed" in result.stdout
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def test_ws2812_accepts_dma_fixed_destination_backpressure(tmp_path: Path) -> None:
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iverilog = shutil.which("iverilog")
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vvp = shutil.which("vvp")
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if iverilog is None or vvp is None:
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return
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memory_map = tmp_path / "memory_map"
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subprocess.run(
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[
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sys.executable,
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str(ROOT / "rtl/mini/address_map/generate_memory_map.py"),
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"--map",
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str(ROOT / "rtl/mini/address_map/memory_map.json"),
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"--output-dir",
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str(memory_map),
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"--have-sram-if",
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"NO",
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],
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check=True,
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)
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common = ROOT / "rtl/managed/clusterip/common/rtl"
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serial = ROOT / "rtl/ip/ribp/serial"
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source_list = tmp_path / "ws2812_dma.fl"
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source_list.write_text(
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"\n".join(
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[
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"+define+SV_ASSRT_DISABLE",
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f"+incdir+{memory_map / 'rtl'}",
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f"+incdir+{common}",
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f"+incdir+{common / 'interface'}",
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f"+incdir+{common / 'utils'}",
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f"+incdir+{ROOT / 'rtl/mini/top'}",
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f"+incdir+{serial}",
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str(common / "interface/ribp_if.sv"),
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str(ROOT / "rtl/mini/top/rib_if.sv"),
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str(common / "utils/register.sv"),
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str(common / "utils/fifo.sv"),
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str(ROOT / "rtl/ip/ribp/peripheral/dma.sv"),
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str(ROOT / "rtl/ip/ribp/peripheral/dma_core.sv"),
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str(serial / "ws2812_if.sv"),
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str(serial / "ws2812_reg.sv"),
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str(serial / "ws2812_core.sv"),
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str(serial / "ribp_ws2812.sv"),
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str(ROOT / "tests/rtl/ws2812_dma_tb.sv"),
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"",
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]
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),
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encoding="utf-8",
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)
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converted = tmp_path / "ws2812_dma_tb.v"
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subprocess.run(
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[
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sys.executable,
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str(ROOT / "rtl/mini/script/convt_sv2v.py"),
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"-f",
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str(source_list),
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"--output",
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str(converted),
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],
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check=True,
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)
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simulation = tmp_path / "ws2812_dma_tb"
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subprocess.run(
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[iverilog, "-g2012", "-s", "ws2812_dma_tb", "-o", str(simulation), str(converted)],
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check=True,
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)
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result = subprocess.run([vvp, str(simulation)], text=True, capture_output=True, check=True)
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assert "WS2812 DMA backpressure integration test passed" in result.stdout
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