mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-04 22:32:36 +00:00
maksyuki
2b6819449c
- Added interface to and implemented error handling for register writes. - Introduced a new test for AXI4 address gate functionality in . - Updated clock and reset domain assertions in to reflect new domain names. - Modified expected outputs in to include new clock domains. - Adjusted chip configuration assertions in to account for additional power pads. - Enhanced memory map tests in with new definitions and includes. - Updated pin mapping tests in to include new reference clock pads. - Improved script tools tests in to ensure correct validation of extension bindings. - Refined system control tests in to include new clock control interface. - Updated USB2 packet RAM tests in to include new SRAM definitions. - Enhanced user extensions tests in to validate new product extension configurations. - Adjusted user IP register parity tests to use legacy extensions. - Updated Yosys synthesis recipe tests to reflect changes in STA period calculations.
17 lines
450 B
Makefile
17 lines
450 B
Makefile
SOC := MINI
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MINI_MODE := MPW
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PDK := IHP130
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HAVE_PLL := NO
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HAVE_SRAM_IF := YES
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HAVE_SRAM_MACRO := YES
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SRAM_SIZE_KIB := 32
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PDK_BEHAV := YES
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HAVE_SVA := NO
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HAVE_HP := NO
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EXT_CLK_HZ := 72000000
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AUD_CLK_HZ := 18432000
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CLINT_TIMEBASE_HZ := 1000000
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ISA := RV32IM
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HAVE_CSR := NO
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APP := bringup
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LINK_TYPE := ld2_psram
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