0 Fork 0

mirror of https://github.com/retroSoC/retroSoC.git synced 2026-11-04 22:32:36 +00:00

Files

T

maksyuki 8ba8a0ad47 feat: add HP mailbox and PLIC tests; enhance existing test coverage

- Updated axi4_interconnect_tb to include an additional master and issue high-priority access tests.
- Introduced hp_mailbox_tb for testing the HP mailbox functionality, including register and doorbell operations.
- Added plic_tb to validate PLIC priority, claim, and completion mechanisms.
- Enhanced pll_ctrl_tb to initialize additional system control signals.
- Updated soc_irq_topology_tb to account for new IRQ sources and validate IRQ signal behavior.
- Improved sysctrl_tb to include tests for HP lifecycle control and status registers.
- Added tests for HP boot bundle layout, CRC, and payload validation.
- Introduced test_hp_mailbox.py for RTL regression testing of the HP mailbox.
- Added test_hp_platform.py to validate HP platform configuration and generated-source boundaries.
- Enhanced test_librelane_flow.py to ensure correct signal placement in chip configuration.
- Added performance log tests to validate LP and HP coremark ratios.
- Updated test_soc_topology.py to reflect changes in IRQ and peripheral mappings.

2026-08-27 19:26:32 +08:00

4.4 KiB

Raw Blame History

Core-Local Interruptor

The baseline Mini SoC CLINT provides machine software and machine timer interrupts for the management hart. The HP profile adds an independent two-slot instance at 0x02000000 and connects slot 1 to HP hart 1. Its register layout follows the conventional SiFive CLINT and RISC-V ACLINT-compatible offsets, while its bus-facing logic uses the retroSoC APB4 target protocol.

Integration

Property	Value
APB4 base address	`0x10020000`
APB4 aperture	64 KiB
Implemented Mini SoC harts	1 management hart
RTL hart parameter range	1 through 4095
Timebase frequency	1 MHz
Management-core interrupts	software IRQ 0, timer IRQ 1
User-core access	denied by the AXI4 interconnect access policy
User-core interrupt visibility	masked

The HP instance uses the same 1 MHz reference timebase. OpenSBI programs hart 1 MSIP at 0x02000004, MTIMECMP at 0x02004008, and shared MTIME at 0x0200BFF8. The baseline management CLINT remains at 0x10020000.

The timebase divider runs from the buffered external reference clock, not the PLL-selected system clock. A toggle crosses into the system domain through the Common edge_det synchronizer and produces one system-clock pulse per microsecond. Consequently, changing the PLL frequency does not change the meaning of an mtime tick. EXT_CLK_HZ must be an integer multiple of CLINT_TIMEBASE_HZ; committed profiles use 72 MHz and 1 MHz respectively.

Register ABI

All implemented registers are 32-bit aligned APB4 accesses. Unmapped, unimplemented-hart, and unaligned accesses complete with resp_err and read as zero. Partial writes use byte strobes. The Mini SoC implements hart 0; the RTL array dimensions and address decoder are parameterized for additional harts.

Offset	Name	Access	Reset	Description
`0x0000 + 4 * hart`	`MSIP`	RW	0	Bit 0 controls the hart machine software interrupt.
`0x4000 + 8 * hart`	`MTIMECMP_LO`	RW	all ones	Low half of the 64-bit timer comparison value.
`0x4004 + 8 * hart`	`MTIMECMP_HI`	RW	all ones	High half of the 64-bit timer comparison value.
`0xBFF8`	`MTIME_LO`	RW	0	Low half of the shared 64-bit time counter.
`0xBFFC`	`MTIME_HI`	RW	0	High half of the shared 64-bit time counter.

The timer interrupt for hart n is asserted when mtime >= mtimecmp[n] and is deasserted after software moves the comparison into the future. The registered interrupt output adds one system-clock cycle of latency. Resetting mtimecmp to all ones prevents an unintended interrupt at reset.

RV32 Software Contract

The public <retrosoc/hal/clint.h> API avoids C 64-bit volatile accesses, which are not atomic on RV32. Time and comparison reads use a bounded high-low-high sequence and retry if the high word rolls over. Comparison writes use the recommended low-all-ones, high, low sequence so an intermediate value cannot spuriously assert the timer interrupt.

Writing mtime itself is inherently non-atomic on a 32-bit bus. Software that changes it must first prevent concurrent timer handling and account for the global discontinuity. Normal scheduling code should leave mtime running and only update mtimecmp.

Verification and Current Scope

The self-checking RTL test instantiates two harts and covers reset values, standard offsets, independent software interrupts, timer comparison, mtime writes, byte strobes, invalid accesses, and synchronized reference-clock ticks. The SBY target proves bounded APB4 response, mtime load/tick/hold priority, registered timer interrupt behavior, and reaches software interrupt, timer interrupt, write-time, and error paths. The ci_smoke firmware checks the standard map through the public HAL before completing the normal SoC boot test.

The current Mini integration does not implement supervisor timer comparison, multiple privilege domains, or per-hart access filtering inside CLINT. Adding those features should use the RISC-V ACLINT MTIMER and MSWI split-device model and a versioned SoC integration update.

The register layout and machine interrupt behavior follow the RISC-V machine timer requirements, the conventional SiFive E31 CLINT map, and the RISC-V ACLINT specification.

4.4 KiB Raw Blame History