mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-04 22:32:36 +00:00
maksyuki
0e36b6a82f
- Added build_hp_rtthread.py for building the RT-Thread kernel with RV64 support. - Updated build_hp_smoke.py to target RV64 architecture and modified output filenames. - Modified generate_vexiiriscv.py to reflect RV64 configuration and memory management. - Created hp_tools.py for shared utilities related to RV64 builds. - Enhanced package_hp_boot.py to package RV64 workloads and updated versioning. - Implemented run_hp_sim.py for executing and validating HP workloads with specific markers. - Developed setup_hp_rtthread.py for installing RT-Thread source and environment setup. - Updated GenerateRetroSocHp.scala to generate RV64 application cores. - Enhanced tests for HP boot bundles, platform specifications, and tool utilities to accommodate RV64 changes. - Adjusted test cases to validate new workload types and ensure compatibility with RV64 architecture.
101 lines
4.4 KiB
Typst
101 lines
4.4 KiB
Typst
#import "../style.typ": *
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#import "../figures.typ": *
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// Publication status is explicit; successful build/tests do not change these marks.
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#let artifact-status = (
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(name:"Available",selected:true),
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(name:"Functional",selected:false),
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(name:"Reproduced",selected:false),
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(name:"Tapedout",selected:false),
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)
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#cover(evaluation:artifact-status)[
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#text(9pt, weight: "semibold", fill: gold)[PRODUCT DATASHEET / #doc.status]
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#v(rhythm.cover-gap)
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#text(30pt, weight: "semibold")[retroSoC Mini]
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#linebreak()
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#text(23pt, weight: "semibold", fill: gold)[Gen2/Gen2+]
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#v(rhythm.cover-gap)
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#text(13pt)[An Open-Source, Linux-Capable Asymmetric Dual-Core SoC]
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#v(rhythm.cover-meta-gap)
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#grid(columns: (1fr, 1fr),
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[*#doc.document_id* · v#doc.version \ #doc.date],
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align(right)[#doc.author \ #doc.maintainer],
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)
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#v(rhythm.cover-rule-gap)
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#line(length:100%, stroke:1.1pt + gold)
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= Product Brief
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== Features
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#columns(2, gutter: rhythm.cover-gutter)[
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#set par(leading: rhythm.cover-leading, spacing: rhythm.cover-spacing)
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#set list(tight:false,spacing:rhythm.cover-list-spacing,body-indent:rhythm.cover-list-indent)
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*Compute and control*
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- Hazard3 LP: boot, clocks, resource ownership and fault recovery.
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- Dual-issue VexiiRiscv HP: RV64IMAFDC + Zicbom, Sv39.
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- JTAG debug; fixed EXT-L control and EXT-H AXI64 slots.
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*Memory and interconnect*
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- 32 KiB banked SRAM in this profile; 4/16/32/64/128 KiB build options.
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- AXI32 control, native AXI64 data paths and APB4 registers.
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- SDRAM, QPI PSRAM and OPI/HyperBus-style external-memory controllers.
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- XPI: four chip selects, 16 LUT sequences, 1/2/4-bit SDR transfers.
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- Eight DMA channels; linked-list TCDs, 16-beat bursts and stream endpoints.
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*Platform services*
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- Two 32-bit timers with 16-bit prescalers; four-channel PWM.
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- 64-bit RTC, two alarms and periodic wake.
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- Window watchdog with early warning and retained reset cause.
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- LP/HP local interrupts, PLIC and mailbox.
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- ARCHINFO, SYSCTRL/RCU, resource ownership and first-fault/performance monitoring.
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#colbreak()
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*Connectivity*
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- 32 GPIOs: atomic outputs, pin interrupts and two alternate-function selections.
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- Two UARTs with 64-byte TX/RX FIFOs; UART0 DMA and RTS/CTS.
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- Two I2C controllers: 7/10-bit addressing and 16-entry command/RX FIFOs.
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- SPI-SD, two 1/4-bit SDR SDIO hosts and bidirectional PS/2.
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- USB2: 8 endpoints, 16 host channels, 16 KiB packet RAM; external ULPI PHY.
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- WS2812: 24-bit GRB with programmable pulse/reset timing.
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*Media and data processing*
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- Stereo 16/24-bit I2S master; 8-bit RGB565/YUV422 DVP with crop/snapshot capture.
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- Baseline JPEG encode/decode up to 2048 × 2048, with private DMA.
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- GA2D fill/copy/convert/opaque blend and A8 masks.
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- APU WAV/FLAC decode; MP3/KWS not advertised.
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- AES-128/192/256, SHA-224/256 and raw RSA-2048; programmable CRC.
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- RNG source remains unqualified for production entropy.
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*Development*
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- Freestanding CRT/HAL and reference apps; simulation, synthesis and timing flows.
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- Experimental Linux integration with separate qualification gates.
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]
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#v(1fr)
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#note(below: 0pt)[This draft describes a reviewed RTL/configuration snapshot. It does not establish silicon
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speed grades, electrical limits, production availability or certification. Gen2/Gen2+ is the
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retained document title; no separate derivative specifications are inferred.]
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]
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#pagebreak()
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== Overview
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retroSoC Mini combines a small management processor with an application processor and shared
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memory and I/O. Hazard3 retains authority over startup, clock transitions, resource ownership
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and fault recovery. VexiiRiscv supplies the application-side compute and Linux integration.
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The design is intended for embedded control, basic human-machine interfaces, retro multimedia
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experimentation, education and ASIC prototyping.
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#figure(product-diagram(), caption:[Integrated Mini PRODUCT IP inventory, organized by function.])<product-diagram>
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#ds-table("profile", [Document reference configuration],
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([Property], [Reference]),
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(
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([Product profile], code(doc.profile)),
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([Hardware source], code(doc.source_revision.slice(0,12))),
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([Technology / SRAM], [IHP130 / 32 KiB, macro interface enabled]),
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([Reset roots], [LP: REF24 at 24 MHz; HP: external 72 MHz]),
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([Audio / PLL], [18.432 MHz input / PLL disabled]),
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([HP boot example], code(doc.hp_profile)),
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([MPW compatibility], code(doc.mpw_profile)),
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), widths:(0.8fr,1.9fr),
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)
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