mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-05 06:32:37 +00:00
- Introduced new CSRs for Hazard3 external interrupts in system_csr.h. - Expanded the IRQ API in irq.h to include external IRQ enable/disable and priority setting functions. - Implemented external IRQ handling in system_irq_handler.c, including registration, enabling, and dispatching. - Created a new source file irq_nocsr.c for CSR-disabled firmware, providing stubs for external IRQ functions. - Updated booter.c to reflect the new external IRQ count in printed specifications. - Modified the soc_topology generation script to accommodate 64-bit IRQ vectors and external IRQ count. - Enhanced the integration tests to validate the new IRQ handling and metadata generation. - Adjusted various files to ensure compatibility with the new external IRQ architecture, including Verilog modules and test cases.
44 lines
1.5 KiB
Systemverilog
44 lines
1.5 KiB
Systemverilog
// Copyright (c) 2023-2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
|
|
// retroSoC is licensed under Mulan PSL v2.
|
|
// You can use this software according to the terms and conditions of the Mulan PSL v2.
|
|
// You may obtain a copy of Mulan PSL v2 at:
|
|
// http://license.coscl.org.cn/MulanPSL2
|
|
// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
|
|
// EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
|
|
// MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.
|
|
// See the Mulan PSL v2 for more details.
|
|
|
|
module core_wrapper #(
|
|
parameter int ExternalIrqCount = 30
|
|
) (
|
|
// verilog_format: off -- preserve reviewed column alignment
|
|
input logic clk_i,
|
|
input logic rst_n_i,
|
|
input logic [ExternalIrqCount+1:0] irq_i,
|
|
input logic jtag_tck_i,
|
|
input logic jtag_tms_i,
|
|
input logic jtag_tdi_i,
|
|
input logic jtag_trst_n_i,
|
|
output logic jtag_tdo_o,
|
|
output logic debug_halted_o,
|
|
axi4_if.master axi4
|
|
// verilog_format: on
|
|
);
|
|
|
|
mgmt_core_wrapper #(
|
|
.ExternalIrqCount(ExternalIrqCount)
|
|
) u_mgmt_core_wrapper (
|
|
.clk_i (clk_i),
|
|
.rst_n_i (rst_n_i),
|
|
.irq_i (irq_i),
|
|
.jtag_tck_i (jtag_tck_i),
|
|
.jtag_tms_i (jtag_tms_i),
|
|
.jtag_tdi_i (jtag_tdi_i),
|
|
.jtag_trst_n_i (jtag_trst_n_i),
|
|
.jtag_tdo_o (jtag_tdo_o),
|
|
.debug_halted_o(debug_halted_o),
|
|
.axi4 (axi4)
|
|
);
|
|
|
|
endmodule
|