mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-06 14:55:14 +00:00
- Updated to integrate a coefficient engine and additional signals for coefficient handling. - Modified to include a coefficient engine, enhancing the encoding process with new signals. - Improved to validate generated blocks against expected values and added timeout handling. - Introduced for testing SRAM wrappers in JPEG workspace. - Enhanced test coverage in to reject invalid STA net drivers. - Updated to ensure proper coverage of canonical domains in timing contracts. - Added a new test for JPEG coefficient engine in . - Improved memory map tests in to validate public active MMIO regions. - Enhanced management core specification tests in to verify high-performance core specifications. - Added behavioral-only checks in to exclude synthesis and netlist consumers. - Updated SDRAM tests in to track active firmware memory. - Enhanced STA constraints tests in to cover current clock domains and net drivers.
179 lines
5.9 KiB
Systemverilog
179 lines
5.9 KiB
Systemverilog
`timescale 1ns / 1ps
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module jpeg_decode_core_tb;
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logic clk = 1'b0;
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logic rst_n = 1'b0;
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logic start;
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logic busy;
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logic done;
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logic [ 15:0] width;
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logic [ 15:0] height;
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logic [ 1:0] sampling;
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logic error_flag;
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logic [ 4:0] error_code;
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logic coefficient_start;
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logic [1535:0] coefficient_block;
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logic [ 511:0] coefficient_quant;
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logic [1599:0] coefficient_reciprocal;
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logic coefficient_start_ready;
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logic [1535:0] coefficient_result;
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logic coefficient_result_valid;
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logic coefficient_result_ready;
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logic coefficient_table_err;
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logic coefficient_overflow;
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logic [ 7:0] input_bytes [0:2047];
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logic [ 7:0] expected_rgb [0:4095];
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integer input_size;
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integer expected_size;
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integer output_index;
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string input_path;
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string expected_path;
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axi4_stream_if #(
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.DATA_WIDTH(64)
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) bitstream_axis (
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.aclk (clk),
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.aresetn(rst_n)
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);
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axi4_stream_if #(
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.DATA_WIDTH(64)
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) pixel_axis (
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.aclk (clk),
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.aresetn(rst_n)
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);
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always #5 clk = ~clk;
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jpeg_coefficient_engine u_coefficient_engine (
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.clk_i (clk),
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.rst_n_i (rst_n),
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.start_i (coefficient_start),
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.decode_i (1'b1),
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.block_i (coefficient_block),
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.quant_i (coefficient_quant),
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.reciprocal_i (coefficient_reciprocal),
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.start_ready_o (coefficient_start_ready),
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.block_o (coefficient_result),
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.result_valid_o(coefficient_result_valid),
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.result_ready_i(coefficient_result_ready),
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.table_err_o (coefficient_table_err),
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.overflow_o (coefficient_overflow)
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);
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jpeg_decode_core #(
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.ExternalCoefficientEngine(1'b1)
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) u_dut (
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.clk_i (clk),
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.rst_n_i (rst_n),
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.start_i (start),
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.output_format_i (3'd2),
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.coefficient_start_o (coefficient_start),
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.coefficient_block_o (coefficient_block),
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.coefficient_quant_o (coefficient_quant),
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.coefficient_reciprocal_o (coefficient_reciprocal),
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.coefficient_start_ready_i (coefficient_start_ready),
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.coefficient_result_i (coefficient_result),
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.coefficient_result_valid_i(coefficient_result_valid),
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.coefficient_result_ready_o(coefficient_result_ready),
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.coefficient_table_err_i (coefficient_table_err),
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.coefficient_overflow_i (coefficient_overflow),
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.bitstream_axis (bitstream_axis),
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.pixel_axis (pixel_axis),
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.start_ready_o (),
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.busy_o (busy),
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.done_o (done),
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.width_o (width),
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.height_o (height),
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.sampling_o (sampling),
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.error_o (error_flag),
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.error_code_o (error_code)
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);
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task automatic send_input_beat(input integer offset_i);
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logic [63:0] data;
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logic [ 7:0] keep;
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begin
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data = '0;
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keep = '0;
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for (int lane = 0; lane < 8; lane++) begin
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if ((offset_i + lane) < input_size) begin
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data[lane*8+:8] = input_bytes[offset_i+lane];
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keep[lane] = 1'b1;
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end
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end
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@(negedge clk);
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bitstream_axis.tdata = data;
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bitstream_axis.tkeep = keep;
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bitstream_axis.tstrb = keep;
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bitstream_axis.tlast = (offset_i + 8) >= input_size;
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bitstream_axis.tvalid = 1'b1;
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@(posedge clk);
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while (!bitstream_axis.tready) @(posedge clk);
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@(negedge clk);
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bitstream_axis.tvalid = 1'b0;
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end
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endtask
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always @(posedge clk) begin
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if (rst_n && pixel_axis.tvalid && pixel_axis.tready) begin
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for (int lane = 0; lane < 8; lane++) begin
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if (pixel_axis.tkeep[lane]) begin
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if (pixel_axis.tdata[lane*8+:8] != expected_rgb[output_index]) begin
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$fatal(1, "decoded byte mismatch at %0d: got=%h expected=%h", output_index,
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pixel_axis.tdata[lane*8+:8], expected_rgb[output_index]);
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end
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output_index = output_index + 1;
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end
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end
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end
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end
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initial begin
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if (!$value$plusargs(
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"input_hex=%s", input_path
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) || !$value$plusargs(
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"input_size=%d", input_size
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) || !$value$plusargs(
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"expected_rgb_hex=%s", expected_path
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) || !$value$plusargs(
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"expected_rgb_size=%d", expected_size
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)) begin
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$fatal(1, "decode core test requires JPEG and RGB plusargs");
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end
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$readmemh(input_path, input_bytes);
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$readmemh(expected_path, expected_rgb);
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start = 1'b0;
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bitstream_axis.tdata = '0;
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bitstream_axis.tkeep = '0;
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bitstream_axis.tstrb = '0;
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bitstream_axis.tlast = 1'b0;
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bitstream_axis.tid = '0;
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bitstream_axis.tdest = '0;
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bitstream_axis.tuser = '0;
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bitstream_axis.tvalid = 1'b0;
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pixel_axis.tready = 1'b1;
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output_index = 0;
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repeat (3) @(posedge clk);
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rst_n = 1'b1;
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@(negedge clk);
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start = 1'b1;
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@(negedge clk);
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start = 1'b0;
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for (int offset = 0; offset < input_size; offset += 8) begin
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send_input_beat(offset);
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end
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for (int cycle = 0; cycle < 200000 && !done && !error_flag; cycle++) begin
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@(negedge clk);
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end
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if (error_flag || !done || width != 16'd16 || height != 16'd16 || sampling != 2'd3 ||
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output_index != expected_size) begin
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$fatal(
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1,
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"decode completion mismatch: done=%0d err=%0d code=%0d size=%0dx%0d sampling=%0d bytes=%0d expected=%0d",
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done, error_flag, error_code, width, height, sampling, output_index, expected_size);
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end
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$display("JPEG decode core tests passed");
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$finish;
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end
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endmodule
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