mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-06 14:55:14 +00:00
maksyuki
98eb8ebad6
- Implemented tests for AXI4 async bridge functionality, including transfer and warm flush scenarios. - Added tests for AXI4 data crossbar to validate concurrent outstanding requests and ACL handling. - Introduced clock frequency monitor tests to ensure detection of clock stop and restart events. - Developed tests for extension DMA master to verify copy operations, tail strobe behavior, and timeout handling. - Created tests for HP lifecycle controller to validate drain, flush, and forced reset functionalities. - Updated existing test scripts to include new RTL components and ensure proper simulation configurations.
281 lines
8.7 KiB
Systemverilog
281 lines
8.7 KiB
Systemverilog
`timescale 1ns / 1ps
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module pll_ctrl_tb;
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logic ext_clk_i = 1'b0;
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logic ref24_clk_i = 1'b0;
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logic aud_clk_i = 1'b0;
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logic rst_n_i = 1'b0;
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logic wdg_reset_req_i = 1'b0;
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logic fault_valid_i = 1'b0;
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logic [31:0] fault_addr_i = '0;
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logic [ 3:0] fault_wstrb_i = '0;
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logic fault_reserved_i = 1'b0;
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logic sys_clk_o;
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logic sys_rst_n_o;
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logic aon_clk_o;
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logic aon_rst_n_o;
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logic hp_clk_o;
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logic hp_rst_n_o;
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logic pclk_o;
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logic pclk_rst_n_o;
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logic mem_clk_o;
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logic mem_rst_n_o;
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logic aud_clk_o;
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logic aud_rst_n_o;
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logic sys_clkdiv4_o;
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apb4_if apb4 (
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.pclk (pclk_o),
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.presetn(pclk_rst_n_o)
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);
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sysctrl_if sysctrl ();
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pll_ctrl_if pll_ctrl ();
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clock_ctrl_if clock_ctrl ();
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logic [31:0] read_data;
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time edge_start;
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time edge_end;
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always #7 ext_clk_i = ~ext_clk_i;
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always #21 ref24_clk_i = ~ref24_clk_i;
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always #27 aud_clk_i = ~aud_clk_i;
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rcu u_rcu (
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.ext_clk_i (ext_clk_i),
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.ref24_clk_i (ref24_clk_i),
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.aud_clk_i (aud_clk_i),
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.ext_rst_n_i (rst_n_i),
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.wdg_reset_req_i(wdg_reset_req_i),
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.hp_idle_i (1'b1),
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.pclk_idle_i (1'b1),
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.pll_ctrl (pll_ctrl),
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.clock_ctrl (clock_ctrl),
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.aon_clk_o (aon_clk_o),
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.aon_rst_n_o (aon_rst_n_o),
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.sys_clk_o (sys_clk_o),
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.sys_rst_n_o (sys_rst_n_o),
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.hp_clk_o (hp_clk_o),
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.hp_rst_n_o (hp_rst_n_o),
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.pclk_o (pclk_o),
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.pclk_rst_n_o (pclk_rst_n_o),
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.mem_clk_o (mem_clk_o),
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.mem_rst_n_o (mem_rst_n_o),
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.aud_clk_o (aud_clk_o),
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.aud_rst_n_o (aud_rst_n_o),
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.sys_clkdiv4_o (sys_clkdiv4_o),
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.timebase_tick_o(),
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.hp_block_o (),
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.pll_fault_o (),
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.mem_pad_mode_o (),
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.mem_pad_lock_o ()
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);
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apb4_sysctrl u_sysctrl (
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.clk_i (pclk_o),
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.rst_n_i (pclk_rst_n_o),
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.fault_valid_i (fault_valid_i),
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.fault_addr_i (fault_addr_i),
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.fault_wstrb_i (fault_wstrb_i),
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.fault_reserved_i(fault_reserved_i),
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.apb4 (apb4),
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.sysctrl (sysctrl),
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.pll_ctrl (pll_ctrl),
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.clock_ctrl (clock_ctrl)
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);
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task automatic read_register(input logic [31:0] address, output logic [31:0] data);
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begin
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@(negedge pclk_o);
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apb4.paddr = address;
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apb4.pwdata = '0;
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apb4.pstrb = '0;
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apb4.pwrite = 1'b0;
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apb4.psel = 1'b1;
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apb4.penable = 1'b0;
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@(negedge pclk_o);
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apb4.penable = 1'b1;
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while (!apb4.pready) @(negedge pclk_o);
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if (apb4.pslverr !== 1'b0) begin
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$fatal(1, "read %h error=%b expected=%b", address, apb4.pslverr, 1'b0);
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end
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data = apb4.prdata;
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apb4.psel = 1'b0;
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apb4.penable = 1'b0;
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end
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endtask
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task automatic write_register(input logic [31:0] address, input logic [31:0] data);
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begin
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@(negedge pclk_o);
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apb4.paddr = address;
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apb4.pwdata = data;
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apb4.pstrb = 4'hF;
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apb4.pwrite = 1'b1;
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apb4.psel = 1'b1;
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apb4.penable = 1'b0;
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@(negedge pclk_o);
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apb4.penable = 1'b1;
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while (!apb4.pready) @(negedge pclk_o);
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if (apb4.pslverr !== 1'b0) begin
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$fatal(1, "write %h error=%b expected=%b", address, apb4.pslverr, 1'b0);
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end
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apb4.psel = 1'b0;
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apb4.penable = 1'b0;
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apb4.pwrite = 1'b0;
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apb4.pstrb = '0;
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end
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endtask
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task automatic wait_for_completion(output logic [31:0] status);
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integer index;
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logic complete;
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begin
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status = '0;
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complete = 1'b0;
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for (index = 0; index < 3000; index = index + 1) begin
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if (!complete) begin
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read_register(32'h1000_B01C, status);
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complete = !status[4];
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end
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end
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if (!complete) begin
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$fatal(1, "pll configuration did not complete");
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end
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end
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endtask
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initial begin
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apb4.psel = 1'b0;
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apb4.paddr = '0;
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apb4.pwdata = '0;
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apb4.pstrb = '0;
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sysctrl.user_bus_idle_i = 1'b1;
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sysctrl.fault_access_i = 1'b0;
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sysctrl.fault_master_i = '0;
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sysctrl.fault_code_i = '0;
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sysctrl.perf_mgmt_wait_i = '0;
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sysctrl.perf_user_wait_i = '0;
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sysctrl.perf_dma_wait_i = '0;
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sysctrl.perf_sdio0_wait_i = '0;
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sysctrl.perf_sdio1_wait_i = '0;
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sysctrl.perf_usb2_wait_i = '0;
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sysctrl.perf_apb4_periph_wait_i = '0;
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sysctrl.perf_apb4_system_wait_i = '0;
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sysctrl.perf_sdram_wait_i = '0;
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sysctrl.perf_psram_wait_i = '0;
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sysctrl.perf_flash_wait_i = '0;
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sysctrl.rtc_wake_i = 1'b0;
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sysctrl.hp_present_i = 1'b0;
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sysctrl.hp_actual_released_i = 1'b0;
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sysctrl.hp_draining_i = 1'b0;
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sysctrl.hp_forced_fault_i = 1'b0;
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rst_n_i = 1'b1;
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#10;
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rst_n_i = 1'b0;
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#100;
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rst_n_i = 1'b1;
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$display("pll_ctrl_tb: root reset released");
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repeat (2) begin
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@(posedge aud_clk_i);
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#1;
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if (aud_clk_o !== 1'b1) begin
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$fatal(1, "buffered audio clock did not follow a rising edge");
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end
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@(negedge aud_clk_i);
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#1;
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if (aud_clk_o !== 1'b0) begin
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$fatal(1, "buffered audio clock did not follow a falling edge");
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end
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end
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$display("pll_ctrl_tb: audio clock buffer passed");
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wait (aud_rst_n_o);
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$display("pll_ctrl_tb: audio reset released");
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repeat (50) @(posedge ref24_clk_i);
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$display("pll_ctrl_tb: lp_clk=%b lp_rst=%b pclk=%b pclk_rst=%b div=%b valid=%b", sys_clk_o,
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sys_rst_n_o, pclk_o, pclk_rst_n_o,
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u_rcu.u_clock_reset_subsystem.u_pclk_divider.s_div_q,
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u_rcu.u_clock_reset_subsystem.s_pclk_cfg_valid);
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wait (pclk_rst_n_o);
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repeat (12) @(posedge pclk_o);
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$display("pll_ctrl_tb: clock domains released");
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if (!$test$plusargs("pll_lock_fail")) begin
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wdg_reset_req_i = 1'b1;
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#1;
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if (aon_rst_n_o !== 1'b1 || sys_rst_n_o || hp_rst_n_o || pclk_rst_n_o || mem_rst_n_o ||
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aud_rst_n_o) begin
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$fatal(1, "watchdog reset did not preserve AON and reset controlled domains");
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end
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wdg_reset_req_i = 1'b0;
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wait (pclk_rst_n_o && sys_rst_n_o && hp_rst_n_o && mem_rst_n_o && aud_rst_n_o);
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if (!aon_rst_n_o) begin
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$fatal(1, "watchdog reset disturbed AON reset");
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end
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$display("pll_ctrl_tb: watchdog reset recovery passed");
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end
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read_register(32'h1000_B01C, read_data);
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`ifdef HAVE_PLL
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if ($test$plusargs("pll_lock_fail")) begin
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if ((read_data !== 32'h0000_0500) && (read_data !== 32'h0000_05A0)) begin
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$fatal(1, "runtime PLL lock fault status mismatch: %h", read_data);
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end
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end else if (read_data !== 32'h0000_0500) begin
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$fatal(1, "pll reset status is not the external safe clock");
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end
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`else
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if (read_data !== 32'h0000_0100) begin
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$fatal(1, "unsupported pll reset status is not the external safe clock");
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end
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`endif
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write_register(32'h1000_B008, 32'd4);
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write_register(32'h1000_B00C, 32'd1);
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$display("pll_ctrl_tb: PLL request submitted");
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wait_for_completion(read_data);
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`ifdef HAVE_PLL
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if ($test$plusargs("pll_lock_fail")) begin
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if (read_data !== 32'h0000_05A0) begin
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$fatal(1, "pll lock timeout did not keep the external safe clock");
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end
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$display("pll controller timeout test passed");
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$finish;
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end
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if (read_data !== 32'h0000_060C) begin
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$fatal(1, "pll configuration did not select the requested frequency");
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end
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repeat (4) @(posedge hp_clk_o);
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@(posedge hp_clk_o);
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edge_start = $time;
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@(posedge hp_clk_o);
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edge_end = $time;
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if ((edge_end - edge_start) > 9) begin
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$fatal(1, "pll behavioral output is slower than 120MHz");
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end
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write_register(32'h1000_B008, 32'd0);
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write_register(32'h1000_B00C, 32'd1);
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wait_for_completion(read_data);
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if (read_data !== 32'h0000_0608) begin
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$fatal(1, "pll did not select the 24MHz profile");
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end
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repeat (4) @(posedge hp_clk_o);
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@(posedge hp_clk_o);
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edge_start = $time;
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@(posedge hp_clk_o);
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edge_end = $time;
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if ((edge_end - edge_start) < 12) begin
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$fatal(1, "pll behavioral output is faster than the 72MHz profile");
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end
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$display("pll controller dynamic configuration test passed");
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`else
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if (read_data !== 32'h0000_0160) begin
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$fatal(1, "unsupported pll backend did not report the safe-clock error");
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end
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$display("pll controller capability gate test passed");
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`endif
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$finish;
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end
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endmodule
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