mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-06 14:55:14 +00:00
maksyuki
2840d22e96
- Updated to integrate a coefficient engine and additional signals for coefficient handling. - Modified to include a coefficient engine, enhancing the encoding process with new signals. - Improved to validate generated blocks against expected values and added timeout handling. - Introduced for testing SRAM wrappers in JPEG workspace. - Enhanced test coverage in to reject invalid STA net drivers. - Updated to ensure proper coverage of canonical domains in timing contracts. - Added a new test for JPEG coefficient engine in . - Improved memory map tests in to validate public active MMIO regions. - Enhanced management core specification tests in to verify high-performance core specifications. - Added behavioral-only checks in to exclude synthesis and netlist consumers. - Updated SDRAM tests in to track active firmware memory. - Enhanced STA constraints tests in to cover current clock domains and net drivers.
106 lines
4.3 KiB
Python
106 lines
4.3 KiB
Python
"""Keep the boot display aligned with the fixed Hazard3 management-core integration."""
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from pathlib import Path
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ROOT = Path(__file__).resolve().parents[1]
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BOOTER = ROOT / "crt/src/service/booter.c"
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SOFTWARE_MAKE = ROOT / "rtl/mini/mk/software.mk"
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MGMT_CORE = ROOT / "rtl/mini/top/mgmt_core_wrapper.sv"
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MGMT_DEBUG = ROOT / "rtl/mini/top/mgmt_debug_wrapper.sv"
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AHBL_TO_AXI4 = ROOT / "rtl/mini/top/ahbl2axi4.sv"
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VEXII_CONFIG = ROOT / "scripts/vexiiriscv/GenerateRetroSocHp.scala"
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def test_booter_prints_the_fixed_hazard3_specification() -> None:
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booter = BOOTER.read_text(encoding="utf-8")
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software_make = SOFTWARE_MAKE.read_text(encoding="utf-8")
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management_core = MGMT_CORE.read_text(encoding="utf-8")
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management_debug = MGMT_DEBUG.read_text(encoding="utf-8")
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ahbl_to_axi4 = AHBL_TO_AXI4.read_text(encoding="utf-8")
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assert "DEF_VAL += -DRS_SOC_MGMT_JTAG_IDCODE=0x$(JTAG_IDCODE)U" in software_make
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assert "Management-Core Specification:" in booter
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assert "Management Processor:" not in booter
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assert "User Processors:" in booter
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assert "Core: Hazard3(single hart), 3-stage pipeline" in booter
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assert "Base: RV32IMAC_Zicsr" in booter
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assert "Bit manipulation: Zba_Zbb_Zbc_Zbkb_Zbkx_Zbs" in booter
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assert "Other: Zifencei_Zilsd_Xh3BextM_Xh3IRQ" in booter
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assert "Not present: U-mode PMP Zcb_Zclsd_Zcmp_Xh3PMPM_Xh3Power" in booter
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assert "IRQ: 30 external + software + timer; Xh3IRQ, 4 priority levels" in booter
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assert "AHB5 manager -> AHB-Lite/AXI4 fabric" in booter
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assert "Single-beat access; no burst or exclusive transactions" in booter
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assert "RS_SOC_MGMT_JTAG_IDCODE" in booter
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assert "RISC-V JTAG DTM/DM, IDCODE 0x%08x" in booter
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assert "One hart: halt/resume, 2 breakpoints; no system-bus access" in booter
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assert "AHB-Lite NSEQ subset" not in booter
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assert "external cache/coherency handshake" not in booter
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assert "TCK/TMS/TDI/TRST_n/TDO" not in booter
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assert "instruction injection" not in booter
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assert "exact execute-address hardware breakpoints" not in booter
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for parameter in (
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".EXTENSION_A (1)",
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".EXTENSION_C (1)",
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".EXTENSION_M (1)",
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".EXTENSION_ZBA (1)",
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".EXTENSION_ZBB (1)",
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".EXTENSION_ZBC (1)",
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".EXTENSION_ZBKB (1)",
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".EXTENSION_ZBKX (1)",
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".EXTENSION_ZBS (1)",
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".EXTENSION_ZIFENCEI (1)",
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".EXTENSION_ZILSD (1)",
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".EXTENSION_XH3BEXTM (1)",
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".EXTENSION_XH3IRQ (1)",
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".U_MODE (0)",
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".PMP_REGIONS (0)",
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".BREAKPOINT_TRIGGERS(2)",
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".NUM_IRQS (30)",
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".IRQ_PRIORITY_BITS (2)",
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):
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assert parameter in management_core
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assert ".HAVE_SBA(0)" in management_debug
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assert "ahbl.htrans == AHBL_TRANS_NSEQ" in ahbl_to_axi4
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assert "axi4.awlen = 8'd0;" in ahbl_to_axi4
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assert "axi4.arlen = 8'd0;" in ahbl_to_axi4
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assert "axi4.awlock = `AXI4_LOCK_NORM;" in ahbl_to_axi4
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assert "axi4.arlock = `AXI4_LOCK_NORM;" in ahbl_to_axi4
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def test_booter_prints_present_hp_core_specification() -> None:
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booter = BOOTER.read_text(encoding="utf-8")
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vexii_config = VEXII_CONFIG.read_text(encoding="utf-8")
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for text in (
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"High-Performance-Core Specification:",
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"Core: VexiiRiscv(hart 1), dual-issue in-order",
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"Base: RV32IMAFDC_Zicbom_Zicntr_Zihpm",
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"Mode: M/S/U; Sv32 MMU, 9-bit ASID",
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"Protection: 16 PMP regions, 4 KiB granularity",
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"L1: separate 16 KiB, 4-way instruction and data caches",
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"Maintenance: 64-byte Zicbom CBO; no hardware coherency",
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"Bus: native AXI64 I/D + cacheless AXI32 MMIO",
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"Embedded RISC-V JTAG, 4 triggers",
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):
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assert text in booter
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assert "rs_sysctrl_get_hp_status(&status)" in booter
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assert "!status.present" in booter
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for parameter in (
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'param.addISA("m", "a", "f", "d", "c", "s", "u", "zicbom", "zicntr", "zihpm")',
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"param.asidWidth = 9",
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"param.decoders = 2",
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"param.lanes = 2",
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"param.fetchL1Sets = 64",
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"param.fetchL1Ways = 4",
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"param.lsuL1Sets = 64",
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"param.lsuL1Ways = 4",
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"param.pmpParam.pmpSize = 16",
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"param.pmpParam.granularity = 4096",
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"param.privParam.debugTriggers = 4",
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):
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assert parameter in vexii_config
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