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retroSoC/crt/include/retrosoc/hal/apu_regs.h
T
maksyuki 57ffd03216 feat: update APU tests to synchronize with P4 ISA and add APU primitives filelist checks 
- Modified test_apu_register_parity.py to reflect changes in P4 ISA definitions.
- Updated test_apu_register_parity.py to include new manifest entries for P4.
- Enhanced test_script_tools.py to include checks for APU primitives filelists.
- Added assertions for APU primitives in the formal filelists test to ensure proper scoping and inclusion.
2026-09-05 07:29:50 +08:00

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#ifndef RETROSOC_HAL_APU_REGS_H
#define RETROSOC_HAL_APU_REGS_H
#include <stdint.h>
#include <retrosoc/core/soc.h>
/* Independently handwritten mirror of rtl/ip/multimedia/apu_define.svh. */
#define RS_APU_ABI_IP_ID UINT32_C(0x000)
#define RS_APU_ABI_IP_VERSION UINT32_C(0x004)
#define RS_APU_ABI_CAPABILITY0 UINT32_C(0x008)
#define RS_APU_ABI_CAPABILITY1 UINT32_C(0x00C)
#define RS_APU_ABI_COMMAND UINT32_C(0x010)
#define RS_APU_ABI_STATUS UINT32_C(0x014)
#define RS_APU_ABI_IRQ_STATE UINT32_C(0x018)
#define RS_APU_ABI_IRQ_ENABLE UINT32_C(0x01C)
#define RS_APU_ABI_IRQ_TEST UINT32_C(0x020)
#define RS_APU_ABI_ERROR_STATUS UINT32_C(0x024)
#define RS_APU_ABI_ERROR_ADDRESS UINT32_C(0x028)
#define RS_APU_ABI_ERROR_DETAIL UINT32_C(0x02C)
#define RS_APU_ABI_SEQUENCER_TIMEOUT UINT32_C(0x030)
#define RS_APU_ABI_STREAM_ROUTE UINT32_C(0x034)
#define RS_APU_ABI_STREAM_STATUS UINT32_C(0x038)
#define RS_APU_ABI_OWNER_STATUS UINT32_C(0x03C)
#define RS_APU_ABI_READ_BASE UINT32_C(0x040)
#define RS_APU_ABI_READ_LIMIT UINT32_C(0x044)
#define RS_APU_ABI_WRITE_BASE UINT32_C(0x048)
#define RS_APU_ABI_WRITE_LIMIT UINT32_C(0x04C)
#define RS_APU_ABI_DMA_TIMEOUT UINT32_C(0x050)
#define RS_APU_ABI_ABI_DIGEST UINT32_C(0x054)
#define RS_APU_ABI_SEQUENCER_STATUS UINT32_C(0x058)
#define RS_APU_ABI_SEQUENCER_RETIRED UINT32_C(0x05C)
#define RS_APU_ABI_STREAM_WATERMARK UINT32_C(0x060)
#define RS_APU_ABI_MC_IMAGE_ADDRESS UINT32_C(0x080)
#define RS_APU_ABI_MC_IMAGE_SIZE UINT32_C(0x084)
#define RS_APU_ABI_MC_EXPECTED_CRC UINT32_C(0x088)
#define RS_APU_ABI_MC_STATUS UINT32_C(0x08C)
#define RS_APU_ABI_MC_ABI UINT32_C(0x090)
#define RS_APU_ABI_MC_BUILD_ID_LO UINT32_C(0x094)
#define RS_APU_ABI_MC_BUILD_ID_HI UINT32_C(0x098)
#define RS_APU_ABI_MC_LOCK UINT32_C(0x09C)
#define RS_APU_ABI_MC_ACTUAL_CRC UINT32_C(0x0A0)
#define RS_APU_ABI_MC_LOAD_COUNT UINT32_C(0x0A4)
#define RS_APU_ABI_JOB_CONTROL UINT32_C(0x100)
#define RS_APU_ABI_JOB_INPUT_ADDRESS UINT32_C(0x104)
#define RS_APU_ABI_JOB_INPUT_LENGTH UINT32_C(0x108)
#define RS_APU_ABI_JOB_OUTPUT_ADDRESS UINT32_C(0x10C)
#define RS_APU_ABI_JOB_OUTPUT_CAPACITY UINT32_C(0x110)
#define RS_APU_ABI_JOB_INPUT_CONFIG UINT32_C(0x114)
#define RS_APU_ABI_JOB_OUTPUT_CONFIG UINT32_C(0x118)
#define RS_APU_ABI_JOB_FLAGS UINT32_C(0x11C)
#define RS_APU_ABI_JOB_STATUS UINT32_C(0x120)
#define RS_APU_ABI_JOB_INPUT_USED UINT32_C(0x124)
#define RS_APU_ABI_JOB_OUTPUT_BYTES UINT32_C(0x128)
#define RS_APU_ABI_JOB_FRAMES UINT32_C(0x12C)
#define RS_APU_ABI_JOB_SOURCE_INFO UINT32_C(0x130)
#define RS_APU_ABI_JOB_CYCLES UINT32_C(0x134)
#define RS_APU_ABI_JOB_DETAIL UINT32_C(0x138)
#define RS_APU_ABI_RING_BASE UINT32_C(0x180)
#define RS_APU_ABI_RING_SIZE UINT32_C(0x184)
#define RS_APU_ABI_RING_HEAD UINT32_C(0x188)
#define RS_APU_ABI_RING_TAIL UINT32_C(0x18C)
#define RS_APU_ABI_RING_CONTROL UINT32_C(0x190)
#define RS_APU_ABI_RING_STATUS UINT32_C(0x194)
#define RS_APU_ABI_RING_COMPLETED UINT32_C(0x198)
#define RS_APU_ABI_RING_COALESCE UINT32_C(0x19C)
#define RS_APU_ABI_RING_DOORBELL UINT32_C(0x1A0)
#define RS_APU_ABI_KWS_MODEL_ADDRESS UINT32_C(0x200)
#define RS_APU_ABI_KWS_MODEL_SIZE UINT32_C(0x204)
#define RS_APU_ABI_KWS_MODEL_EXPECTED_CRC UINT32_C(0x208)
#define RS_APU_ABI_KWS_CONTROL UINT32_C(0x20C)
#define RS_APU_ABI_KWS_CONFIG UINT32_C(0x210)
#define RS_APU_ABI_KWS_STATUS UINT32_C(0x214)
#define RS_APU_ABI_KWS_RESULT UINT32_C(0x218)
#define RS_APU_ABI_KWS_TIMESTAMP_LO UINT32_C(0x21C)
#define RS_APU_ABI_KWS_TIMESTAMP_HI UINT32_C(0x220)
#define RS_APU_ABI_KWS_FRAME_COUNT UINT32_C(0x224)
#define RS_APU_ABI_KWS_INFERENCE_COUNT UINT32_C(0x228)
#define RS_APU_ABI_KWS_HIT_COUNT UINT32_C(0x22C)
#define RS_APU_ABI_KWS_OVERRUN_COUNT UINT32_C(0x230)
#define RS_APU_ABI_KWS_MODEL_STATUS UINT32_C(0x234)
#define RS_APU_ABI_KWS_MODEL_ACTUAL_CRC UINT32_C(0x238)
#define RS_APU_ABI_PERF_CONTROL UINT32_C(0x300)
#define RS_APU_ABI_PERF_STATUS UINT32_C(0x304)
#define RS_APU_ABI_PERF_ACTIVE_CYCLES_LO UINT32_C(0x308)
#define RS_APU_ABI_PERF_ACTIVE_CYCLES_HI UINT32_C(0x30C)
#define RS_APU_ABI_PERF_INPUT_BYTES_LO UINT32_C(0x310)
#define RS_APU_ABI_PERF_INPUT_BYTES_HI UINT32_C(0x314)
#define RS_APU_ABI_PERF_OUTPUT_BYTES_LO UINT32_C(0x318)
#define RS_APU_ABI_PERF_OUTPUT_BYTES_HI UINT32_C(0x31C)
#define RS_APU_ABI_PERF_DECODED_FRAMES_LO UINT32_C(0x320)
#define RS_APU_ABI_PERF_DECODED_FRAMES_HI UINT32_C(0x324)
#define RS_APU_ABI_PERF_DMA_READ_STALLS_LO UINT32_C(0x328)
#define RS_APU_ABI_PERF_DMA_READ_STALLS_HI UINT32_C(0x32C)
#define RS_APU_ABI_PERF_DMA_WRITE_STALLS_LO UINT32_C(0x330)
#define RS_APU_ABI_PERF_DMA_WRITE_STALLS_HI UINT32_C(0x334)
#define RS_APU_ABI_PERF_STREAM_STALLS_LO UINT32_C(0x338)
#define RS_APU_ABI_PERF_STREAM_STALLS_HI UINT32_C(0x33C)
#define RS_APU_ABI_PERF_SEQUENCER_INSTR_LO UINT32_C(0x340)
#define RS_APU_ABI_PERF_SEQUENCER_INSTR_HI UINT32_C(0x344)
#define RS_APU_ABI_PERF_KWS_CYCLES_LO UINT32_C(0x348)
#define RS_APU_ABI_PERF_KWS_CYCLES_HI UINT32_C(0x34C)
#define RS_APU_ABI_PERF_FAULTS_LO UINT32_C(0x350)
#define RS_APU_ABI_PERF_FAULTS_HI UINT32_C(0x354)
#define RS_APU_ABI_CAPABILITY0_WAV 0U
#define RS_APU_ABI_CAPABILITY0_MP3 1U
#define RS_APU_ABI_CAPABILITY0_FLAC 2U
#define RS_APU_ABI_CAPABILITY0_PRIVATE_DMA 3U
#define RS_APU_ABI_CAPABILITY0_RING 4U
#define RS_APU_ABI_CAPABILITY0_STREAMS 5U
#define RS_APU_ABI_CAPABILITY0_KWS 6U
#define RS_APU_ABI_CAPABILITY0_SEQUENCER 7U
#define RS_APU_ABI_CAPABILITY0_RESAMPLER 8U
#define RS_APU_ABI_CAPABILITY1_CONTROL_KIB 0U
#define RS_APU_ABI_CAPABILITY1_DATA_KIB 8U
#define RS_APU_ABI_CAPABILITY1_MAX_CHANNELS 16U
#define RS_APU_ABI_CAPABILITY1_MAX_RATE_KHZ 18U
#define RS_APU_ABI_COMMAND_START_DIRECT 0U
#define RS_APU_ABI_COMMAND_ABORT 1U
#define RS_APU_ABI_COMMAND_SOFT_RESET 2U
#define RS_APU_ABI_COMMAND_RING_KICK 3U
#define RS_APU_ABI_COMMAND_MICROCODE_LOAD 4U
#define RS_APU_ABI_COMMAND_MODEL_LOAD 5U
#define RS_APU_ABI_COMMAND_CLEAR_COUNTERS 6U
#define RS_APU_ABI_STATUS_MICROCODE_VALID 0U
#define RS_APU_ABI_STATUS_MODEL_VALID 1U
#define RS_APU_ABI_STATUS_BUSY 2U
#define RS_APU_ABI_STATUS_RING 3U
#define RS_APU_ABI_STATUS_DECODE 4U
#define RS_APU_ABI_STATUS_KWS_LISTENING 5U
#define RS_APU_ABI_STATUS_QUIESCED 6U
#define RS_APU_ABI_STATUS_ABORTING 7U
#define RS_APU_ABI_STATUS_IDLE 8U
#define RS_APU_ABI_STATUS_SEQUENCER_TRAPPED 9U
#define RS_APU_ABI_STREAM_STATUS_TX_ACTIVE 0U
#define RS_APU_ABI_STREAM_STATUS_RX_ACTIVE 1U
#define RS_APU_ABI_STREAM_STATUS_TX_EMPTY 2U
#define RS_APU_ABI_STREAM_STATUS_TX_FULL 3U
#define RS_APU_ABI_STREAM_STATUS_RX_EMPTY 4U
#define RS_APU_ABI_STREAM_STATUS_RX_FULL 5U
#define RS_APU_ABI_STREAM_STATUS_TX_UNDERRUN 6U
#define RS_APU_ABI_STREAM_STATUS_RX_OVERRUN 7U
#define RS_APU_ABI_STREAM_STATUS_TX_COUNT 8U
#define RS_APU_ABI_STREAM_STATUS_RX_COUNT 16U
#define RS_APU_ABI_STREAM_WATERMARK_RX_HIGH 0U
#define RS_APU_ABI_STREAM_WATERMARK_TX_LOW 8U
#define RS_APU_ABI_IRQ_DIRECT_DONE 0U
#define RS_APU_ABI_IRQ_RING_EVENT 1U
#define RS_APU_ABI_IRQ_KWS_HIT 2U
#define RS_APU_ABI_IRQ_MICROCODE_LOAD_DONE 3U
#define RS_APU_ABI_IRQ_MODEL_LOAD_DONE 4U
#define RS_APU_ABI_IRQ_ABORT_DONE 5U
#define RS_APU_ABI_IRQ_INPUT_WATERMARK 6U
#define RS_APU_ABI_IRQ_OUTPUT_WATERMARK 7U
#define RS_APU_ABI_IRQ_FIRST_ERROR 8U
#define RS_APU_ABI_IRQ_STREAM_XRUN 9U
#define RS_APU_ABI_IRQ_SEQUENCER_TRAP 10U
#define RS_APU_ABI_ERROR_VALID 0U
#define RS_APU_ABI_ERROR_CODE 1U
#define RS_APU_ABI_ERROR_STAGE 7U
#define RS_APU_ABI_ERROR_AXI_RESPONSE 11U
#define RS_APU_ABI_ERROR_DESCRIPTOR_INDEX 13U
#define RS_APU_ABI_ERROR_CODE_NONE 0U
#define RS_APU_ABI_ERROR_CODE_INVALID_CONFIG 1U
#define RS_APU_ABI_ERROR_CODE_INVALID_RING 2U
#define RS_APU_ABI_ERROR_CODE_UNSUPPORTED 3U
#define RS_APU_ABI_ERROR_CODE_MALFORMED 4U
#define RS_APU_ABI_ERROR_CODE_TRUNCATED 5U
#define RS_APU_ABI_ERROR_CODE_CODEC_CRC 6U
#define RS_APU_ABI_ERROR_CODE_DECODE 7U
#define RS_APU_ABI_ERROR_CODE_RECONSTRUCTION 8U
#define RS_APU_ABI_ERROR_CODE_MICROCODE 9U
#define RS_APU_ABI_ERROR_CODE_MICROCODE_CRC 10U
#define RS_APU_ABI_ERROR_CODE_SEQUENCER 11U
#define RS_APU_ABI_ERROR_CODE_KWS_MODEL 12U
#define RS_APU_ABI_ERROR_CODE_KWS_CRC 13U
#define RS_APU_ABI_ERROR_CODE_KWS_ARITHMETIC 14U
#define RS_APU_ABI_ERROR_CODE_AXI_READ 15U
#define RS_APU_ABI_ERROR_CODE_AXI_WRITE 16U
#define RS_APU_ABI_ERROR_CODE_DMA_TIMEOUT 17U
#define RS_APU_ABI_ERROR_CODE_STREAM_UNDERRUN 18U
#define RS_APU_ABI_ERROR_CODE_STREAM_OVERRUN 19U
#define RS_APU_ABI_ERROR_CODE_ABORT 20U
#define RS_APU_ABI_ERROR_CODE_RESOURCE_RESET 21U
#define RS_APU_ABI_ERROR_CODE_OVERFLOW 22U
#define RS_APU_ABI_ERROR_STAGE_APB 0U
#define RS_APU_ABI_ERROR_STAGE_LOADER 1U
#define RS_APU_ABI_ERROR_STAGE_RING 2U
#define RS_APU_ABI_ERROR_STAGE_DMA_READ 3U
#define RS_APU_ABI_ERROR_STAGE_BITSTREAM 4U
#define RS_APU_ABI_ERROR_STAGE_ENTROPY 5U
#define RS_APU_ABI_ERROR_STAGE_RECONSTRUCTION 6U
#define RS_APU_ABI_ERROR_STAGE_RESAMPLER 7U
#define RS_APU_ABI_ERROR_STAGE_DMA_WRITE 8U
#define RS_APU_ABI_ERROR_STAGE_KWS_FRONTEND 9U
#define RS_APU_ABI_ERROR_STAGE_KWS_INFERENCE 10U
#define RS_APU_ABI_ERROR_STAGE_LIFECYCLE 11U
#define RS_APU_ABI_OWNER_STATUS_OWNER 0U
#define RS_APU_ABI_OWNER_STATUS_LOCK 8U
#define RS_APU_ABI_OWNER_STATUS_QUIESCE 9U
#define RS_APU_ABI_OWNER_STATUS_RESET 10U
#define RS_APU_ABI_JOB_STATUS_BUSY 0U
#define RS_APU_ABI_JOB_STATUS_DONE 1U
#define RS_APU_ABI_JOB_STATUS_ERROR 2U
#define RS_APU_ABI_JOB_STATUS_ABORTED 3U
#define RS_APU_ABI_JOB_STATUS_DIRECT_ACTIVE 4U
#define RS_APU_ABI_JOB_STATUS_INPUT_PENDING 5U
#define RS_APU_ABI_JOB_STATUS_OUTPUT_PENDING 6U
#define RS_APU_ABI_JOB_STATUS_WRITEBACK_PENDING 7U
#define RS_APU_ABI_JOB_STATUS_ERROR_CODE 8U
#define RS_APU_ABI_JOB_STATUS_STAGE 14U
#define RS_APU_ABI_JOB_STATUS_AXI_RESPONSE 18U
#define RS_APU_ABI_RING_STATUS_ACTIVE 0U
#define RS_APU_ABI_RING_STATUS_STALLED_UNOWNED 1U
#define RS_APU_ABI_RING_STATUS_EMPTY 2U
#define RS_APU_ABI_RING_STATUS_ERROR 3U
#define RS_APU_ABI_RING_STATUS_WRAPPED 4U
#define RS_APU_ABI_RING_STATUS_COALESCE_PENDING 5U
#define RS_APU_ABI_RING_STATUS_WRITEBACK_PENDING 6U
#define RS_APU_ABI_RING_STATUS_STOPPED_ON_ERROR 7U
#define RS_APU_ABI_RING_STATUS_PENDING_COUNT 8U
#define RS_APU_ABI_RING_STATUS_LAST_INDEX 16U
#define RS_APU_ABI_DESCRIPTOR_WORDS 32U
#define RS_APU_ABI_DESCRIPTOR_BYTES 128U
#define RS_APU_ABI_DESCRIPTOR_ALIGNMENT 128U
#define RS_APU_ABI_DESCRIPTOR_CONTROL 0U
#define RS_APU_ABI_DESCRIPTOR_RESULT_STATUS 1U
#define RS_APU_ABI_DESCRIPTOR_INPUT_ADDRESS 2U
#define RS_APU_ABI_DESCRIPTOR_INPUT_LENGTH 3U
#define RS_APU_ABI_DESCRIPTOR_OUTPUT_ADDRESS 4U
#define RS_APU_ABI_DESCRIPTOR_OUTPUT_CAPACITY 5U
#define RS_APU_ABI_DESCRIPTOR_INPUT_CONFIG 6U
#define RS_APU_ABI_DESCRIPTOR_OUTPUT_CONFIG 7U
#define RS_APU_ABI_DESCRIPTOR_JOB_FLAGS 8U
#define RS_APU_ABI_DESCRIPTOR_KWS_CONFIG 9U
#define RS_APU_ABI_DESCRIPTOR_RESULT_INPUT_USED 10U
#define RS_APU_ABI_DESCRIPTOR_RESULT_OUTPUT_BYTES 11U
#define RS_APU_ABI_DESCRIPTOR_RESULT_FRAMES 12U
#define RS_APU_ABI_DESCRIPTOR_RESULT_SOURCE_INFO 13U
#define RS_APU_ABI_DESCRIPTOR_RESULT_CYCLES 14U
#define RS_APU_ABI_DESCRIPTOR_RESULT_DETAIL 15U
#define RS_APU_ABI_DESCRIPTOR_COOKIE_LO 16U
#define RS_APU_ABI_DESCRIPTOR_COOKIE_HI 17U
#define RS_APU_ABI_DESCRIPTOR_START_TIMESTAMP_LO 18U
#define RS_APU_ABI_DESCRIPTOR_START_TIMESTAMP_HI 19U
#define RS_APU_ABI_DESCRIPTOR_FINISH_TIMESTAMP_LO 20U
#define RS_APU_ABI_DESCRIPTOR_FINISH_TIMESTAMP_HI 21U
#define RS_APU_ABI_DESCRIPTOR_KWS_RESULT 22U
#define RS_APU_ABI_DESCRIPTOR_MICROCODE_BUILD_ID 23U
#define RS_APU_ABI_DESCRIPTOR_CONTROL_OPERATION 0U
#define RS_APU_ABI_DESCRIPTOR_CONTROL_INPUT_FORMAT 4U
#define RS_APU_ABI_DESCRIPTOR_CONTROL_OUTPUT_MODE 8U
#define RS_APU_ABI_DESCRIPTOR_CONTROL_DOWNMIX 10U
#define RS_APU_ABI_DESCRIPTOR_CONTROL_RESAMPLE 11U
#define RS_APU_ABI_DESCRIPTOR_CONTROL_IOC 30U
#define RS_APU_ABI_DESCRIPTOR_CONTROL_OWN 31U
#define RS_APU_ABI_DESCRIPTOR_STATUS_DONE 0U
#define RS_APU_ABI_DESCRIPTOR_STATUS_ERROR 1U
#define RS_APU_ABI_DESCRIPTOR_STATUS_ABORTED 2U
#define RS_APU_ABI_DESCRIPTOR_STATUS_ERROR_CODE 3U
#define RS_APU_ABI_DESCRIPTOR_STATUS_STAGE 9U
#define RS_APU_ABI_DESCRIPTOR_STATUS_AXI_RESPONSE 13U
#define RS_APU_ABI_PERF_CONTROL_ENABLE 0U
#define RS_APU_ABI_PERF_CONTROL_CLEAR 1U
#define RS_APU_ABI_PERF_CONTROL_SNAPSHOT 2U
#define RS_APU_ABI_PERF_STATUS_SNAPSHOT_VALID 0U
#define RS_APU_ABI_MC_STATUS_BUSY 0U
#define RS_APU_ABI_MC_STATUS_VALID 1U
#define RS_APU_ABI_MC_STATUS_HEADER_ERROR 2U
#define RS_APU_ABI_MC_STATUS_RANGE_ERROR 3U
#define RS_APU_ABI_MC_STATUS_CONTROL_ERROR 4U
#define RS_APU_ABI_MC_STATUS_TABLE_ERROR 5U
#define RS_APU_ABI_MC_STATUS_CRC_ERROR 6U
#define RS_APU_ABI_MC_STATUS_CAPABILITY_ERROR 7U
#define RS_APU_ABI_MC_LOCK_LOCKED 0U
#define RS_APU_ABI_SEQUENCER_STATUS_PC 0U
#define RS_APU_ABI_SEQUENCER_STATUS_CLASS 11U
#define RS_APU_ABI_SEQUENCER_STATUS_OPCODE 15U
#define RS_APU_ABI_SEQUENCER_STATUS_WAIT 19U
#define RS_APU_ABI_SEQUENCER_STATUS_LOOP 20U
#define RS_APU_ABI_APUMC_MAGIC UINT32_C(0x41504D43)
#define RS_APU_ABI_APUMC_ABI UINT32_C(0x00010000)
#define RS_APU_ABI_APUMC_HEADER_BYTES 64U
#define RS_APU_ABI_APUMC_HEADER_WORDS 16U
#define RS_APU_ABI_APUMC_ENTRY_BYTES 32U
#define RS_APU_ABI_APUMC_ENTRY_WORDS 8U
#define RS_APU_ABI_APUMC_ENTRY_COUNT 3U
#define RS_APU_ABI_APUMC_MAX_INSTRUCTIONS 2048U
#define RS_APU_ABI_APUMC_P3_PRIMITIVE_MASK UINT32_C(0x00000000)
#define RS_APU_ABI_APUMC_P4_PRIMITIVE_MASK UINT32_C(0x0000FFFF)
#define RS_APU_ABI_LOCAL_DATA_BYTES 114688U
#define RS_APU_ABI_LOCAL_CODEC_BYTES 40960U
#define RS_APU_ABI_LOCAL_TABLE_SCRATCH_BYTES 24576U
#define RS_APU_ABI_LOCAL_INPUT_BASE 24576U
#define RS_APU_ABI_LOCAL_OUTPUT_BASE 32768U
#define RS_APU_ABI_LOCAL_KWS_BASE 40960U
#define RS_APU_ABI_LOCAL_INTERNAL_BASE 106496U
#define RS_APU_ABI_APUMC_HEADER_MAGIC 0U
#define RS_APU_ABI_APUMC_HEADER_ABI 1U
#define RS_APU_ABI_APUMC_HEADER_TOTAL_BYTES 2U
#define RS_APU_ABI_APUMC_HEADER_INSTRUCTIONS 3U
#define RS_APU_ABI_APUMC_HEADER_INSTR_OFFSET 4U
#define RS_APU_ABI_APUMC_HEADER_TABLE_OFFSET 5U
#define RS_APU_ABI_APUMC_HEADER_TABLE_BYTES 6U
#define RS_APU_ABI_APUMC_HEADER_ENTRY_OFFSET 7U
#define RS_APU_ABI_APUMC_HEADER_ENTRY_COUNT 8U
#define RS_APU_ABI_APUMC_HEADER_PRIMITIVES 9U
#define RS_APU_ABI_APUMC_HEADER_SCRATCH_END 10U
#define RS_APU_ABI_APUMC_HEADER_CRC 11U
#define RS_APU_ABI_APUMC_HEADER_BUILD_LO 12U
#define RS_APU_ABI_APUMC_HEADER_BUILD_HI 13U
#define RS_APU_ABI_APUMC_ENTRY_FORMAT_PC 0U
#define RS_APU_ABI_APUMC_ENTRY_RANGE 1U
#define RS_APU_ABI_APUMC_ENTRY_SCRATCH_BASE 2U
#define RS_APU_ABI_APUMC_ENTRY_SCRATCH_BYTES 3U
#define RS_APU_ABI_APUMC_ENTRY_MAX_LOOP 4U
#define RS_APU_ABI_APUMC_ENTRY_MAX_RETIRED 5U
#define RS_APU_ABI_APUMC_ENTRY_PRIMITIVES 6U
#define RS_APU_ABI_APUMC_ENTRY_TABLE 7U
#define RS_APU_ABI_MC_INSTRUCTION_IMMEDIATE 0U
#define RS_APU_ABI_MC_INSTRUCTION_AUX 32U
#define RS_APU_ABI_MC_INSTRUCTION_SRC1 40U
#define RS_APU_ABI_MC_INSTRUCTION_SRC0 44U
#define RS_APU_ABI_MC_INSTRUCTION_DST 48U
#define RS_APU_ABI_MC_INSTRUCTION_PREDICATE 52U
#define RS_APU_ABI_MC_INSTRUCTION_OPCODE 56U
#define RS_APU_ABI_MC_INSTRUCTION_CLASS 60U
#define RS_APU_ABI_MC_CLASS_CONTROL 0U
#define RS_APU_ABI_MC_CLASS_SCALAR 1U
#define RS_APU_ABI_MC_CLASS_BITSTREAM 2U
#define RS_APU_ABI_MC_CLASS_ENTROPY 3U
#define RS_APU_ABI_MC_CLASS_LOCAL 4U
#define RS_APU_ABI_MC_CLASS_KERNEL 5U
#define RS_APU_ABI_MC_CLASS_TRANSPORT 6U
#define RS_APU_ABI_MC_CONTROL_NOP 0U
#define RS_APU_ABI_MC_CONTROL_END 1U
#define RS_APU_ABI_MC_CONTROL_TRAP 2U
#define RS_APU_ABI_MC_CONTROL_JUMP_FWD 3U
#define RS_APU_ABI_MC_CONTROL_CALL_FWD 4U
#define RS_APU_ABI_MC_CONTROL_RET 5U
#define RS_APU_ABI_MC_CONTROL_LOOP_SETUP 6U
#define RS_APU_ABI_MC_CONTROL_LOOP_BACK 7U
#define RS_APU_ABI_MC_CONTROL_WAIT 8U
#define RS_APU_ABI_MC_SCALAR_MOV 0U
#define RS_APU_ABI_MC_SCALAR_MOVI 1U
#define RS_APU_ABI_MC_SCALAR_ADD 2U
#define RS_APU_ABI_MC_SCALAR_SUB 3U
#define RS_APU_ABI_MC_SCALAR_AND 4U
#define RS_APU_ABI_MC_SCALAR_OR 5U
#define RS_APU_ABI_MC_SCALAR_XOR 6U
#define RS_APU_ABI_MC_SCALAR_SHL 7U
#define RS_APU_ABI_MC_SCALAR_SHR 8U
#define RS_APU_ABI_MC_SCALAR_SAR 9U
#define RS_APU_ABI_MC_SCALAR_CMP 10U
#define RS_APU_ABI_MC_SCALAR_MIN 11U
#define RS_APU_ABI_MC_SCALAR_MAX 12U
#define RS_APU_ABI_MC_SCALAR_SAT 13U
#define RS_APU_ABI_MC_BITSTREAM_REFILL 0U
#define RS_APU_ABI_MC_BITSTREAM_PEEK 1U
#define RS_APU_ABI_MC_BITSTREAM_GET 2U
#define RS_APU_ABI_MC_BITSTREAM_SKIP 3U
#define RS_APU_ABI_MC_BITSTREAM_ALIGN 4U
#define RS_APU_ABI_MC_BITSTREAM_FRAME_SYNC 5U
#define RS_APU_ABI_MC_BITSTREAM_CRC8 6U
#define RS_APU_ABI_MC_BITSTREAM_CRC16 7U
#define RS_APU_ABI_MC_ENTROPY_HUFF_SYMBOL 0U
#define RS_APU_ABI_MC_ENTROPY_HUFF_PAIR 1U
#define RS_APU_ABI_MC_ENTROPY_HUFF_QUAD 2U
#define RS_APU_ABI_MC_ENTROPY_UNARY 3U
#define RS_APU_ABI_MC_ENTROPY_RICE4 4U
#define RS_APU_ABI_MC_ENTROPY_RICE5 5U
#define RS_APU_ABI_MC_ENTROPY_SIGN_RESTORE 6U
#define RS_APU_ABI_MC_LOCAL_LD32 0U
#define RS_APU_ABI_MC_LOCAL_ST32 1U
#define RS_APU_ABI_MC_LOCAL_TABLE8 2U
#define RS_APU_ABI_MC_LOCAL_TABLE16 3U
#define RS_APU_ABI_MC_LOCAL_TABLE32 4U
#define RS_APU_ABI_MC_LOCAL_FIFO_POP 5U
#define RS_APU_ABI_MC_LOCAL_FIFO_PUSH 6U
#define RS_APU_ABI_MC_KERNEL_REQUANT 0U
#define RS_APU_ABI_MC_KERNEL_STEREO 1U
#define RS_APU_ABI_MC_KERNEL_IMDCT6 2U
#define RS_APU_ABI_MC_KERNEL_IMDCT18 3U
#define RS_APU_ABI_MC_KERNEL_DCT32_POLY 4U
#define RS_APU_ABI_MC_KERNEL_FIXED 5U
#define RS_APU_ABI_MC_KERNEL_LPC 6U
#define RS_APU_ABI_MC_KERNEL_DECORRELATE 7U
#define RS_APU_ABI_MC_KERNEL_RESAMPLE 8U
#define RS_APU_ABI_MC_KERNEL_PCM_PACK 9U
#define RS_APU_ABI_MC_TRANSPORT_INPUT_REFILL 0U
#define RS_APU_ABI_MC_TRANSPORT_OUTPUT_COMMIT 1U
#define RS_APU_ABI_MC_TRANSPORT_OUTPUT_STREAM 2U
#define RS_APU_ABI_MC_TRANSPORT_DMA_WAIT 3U
#define RS_APU_ABI_MC_TRANSPORT_FRAME_COMMIT 4U
#define RS_APU_ABI_MC_TRANSPORT_JOB_RESULT 5U
#define RS_APU_ABI_MC_TRANSPORT_EVENT 6U
#define RS_APU_ABI_MC_PRED_ALWAYS 0U
#define RS_APU_ABI_MC_PRED_EQ 1U
#define RS_APU_ABI_MC_PRED_NE 2U
#define RS_APU_ABI_MC_PRED_SIGNED_LT 3U
#define RS_APU_ABI_MC_PRED_SIGNED_GE 4U
#define RS_APU_ABI_MC_PRED_UNSIGNED_LT 5U
#define RS_APU_ABI_MC_PRED_UNSIGNED_GE 6U
#define RS_APU_ABI_MC_PRED_INPUT_EXHAUSTED 7U
#define RS_APU_ABI_MC_PRED_INPUT_READY 8U
#define RS_APU_ABI_MC_PRED_OUTPUT_READY 9U
#define RS_APU_ABI_MC_PRED_KERNEL_DONE 10U
#define RS_APU_ABI_MC_PRED_TRANSPORT_DONE 11U
#define RS_APU_ABI_MC_WAIT_DMA 0U
#define RS_APU_ABI_MC_WAIT_KERNEL 1U
#define RS_APU_ABI_MC_WAIT_INPUT_FIFO 2U
#define RS_APU_ABI_MC_WAIT_OUTPUT_FIFO 3U
#define RS_APU_ABI_MC_WAIT_TX_STREAM 4U
#define RS_APU_ABI_MC_WAIT_RING_WRITEBACK 5U
#define RS_APU_ABI_MC_PRIMITIVE_BITSTREAM 0U
#define RS_APU_ABI_MC_PRIMITIVE_CRC 1U
#define RS_APU_ABI_MC_PRIMITIVE_HUFFMAN 2U
#define RS_APU_ABI_MC_PRIMITIVE_RICE 3U
#define RS_APU_ABI_MC_PRIMITIVE_LOCAL_MEMORY 4U
#define RS_APU_ABI_MC_PRIMITIVE_LOCAL_FIFO 5U
#define RS_APU_ABI_MC_PRIMITIVE_REQUANTIZE 6U
#define RS_APU_ABI_MC_PRIMITIVE_STEREO 7U
#define RS_APU_ABI_MC_PRIMITIVE_IMDCT6 8U
#define RS_APU_ABI_MC_PRIMITIVE_IMDCT18 9U
#define RS_APU_ABI_MC_PRIMITIVE_DCT32_POLY 10U
#define RS_APU_ABI_MC_PRIMITIVE_FIXED 11U
#define RS_APU_ABI_MC_PRIMITIVE_LPC 12U
#define RS_APU_ABI_MC_PRIMITIVE_DECORRELATE 13U
#define RS_APU_ABI_MC_PRIMITIVE_RESAMPLER 14U
#define RS_APU_ABI_MC_PRIMITIVE_PCM_PACK 15U
#define RS_APU_ABI_MC_PRIMITIVE_DMA_INPUT 16U
#define RS_APU_ABI_MC_PRIMITIVE_DMA_OUTPUT 17U
#define RS_APU_ABI_MC_PRIMITIVE_STREAM_OUTPUT 18U
#define RS_APU_ABI_MC_PRIMITIVE_FRAME_COMMIT 19U
#define RS_APU_ABI_MC_PRIMITIVE_EVENT 20U
#define RS_APU_ABI_MC_TRAP_ILLEGAL 1U
#define RS_APU_ABI_MC_TRAP_PC_RANGE 2U
#define RS_APU_ABI_MC_TRAP_CALL_STACK 3U
#define RS_APU_ABI_MC_TRAP_LOOP 4U
#define RS_APU_ABI_MC_TRAP_LOCAL_RANGE 5U
#define RS_APU_ABI_MC_TRAP_UNAVAILABLE 6U
#define RS_APU_ABI_MC_TRAP_WATCHDOG 7U
#define RS_APU_ABI_MC_TRAP_RETIRED_BUDGET 8U
#define RS_APU_ABI_MC_TRAP_ENGINE 9U
#define RS_APU_ABI_MC_TRAP_EXPLICIT 10U
#define RS_APU_IP_ID_VALUE UINT32_C(0x41505530)
#define RS_APU_IP_VERSION_VALUE UINT32_C(0x00010000)
#define RS_APU_IP_VERSION_MAJOR_MASK UINT32_C(0xFFFF0000)
#define RS_APU_CAPABILITY0_IMPLEMENTED UINT32_C(0x00000198)
#define RS_APU_CAPABILITY1_IMPLEMENTED UINT32_C(0x01827010)
#define RS_APU_DIGEST_IMPLEMENTED UINT32_C(0x00000000)
#define RS_APU_IRQ_ALL UINT32_C(0x000007FF)
#define RS_APU_REG_IP_ID RS_APU_ABI_IP_ID
#define RS_APU_REG_IP_VERSION RS_APU_ABI_IP_VERSION
#define RS_APU_REG_CAPABILITY0 RS_APU_ABI_CAPABILITY0
#define RS_APU_REG_CAPABILITY1 RS_APU_ABI_CAPABILITY1
#define RS_APU_REG_ABI_DIGEST RS_APU_ABI_ABI_DIGEST
#define RS_APU_REG(offset) RS_SOC_REG32(RS_SOC_APB4_APU_BASE, (offset))
#endif
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