mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-06 14:55:14 +00:00
maksyuki
57ffd03216
- Modified test_apu_register_parity.py to reflect changes in P4 ISA definitions. - Updated test_apu_register_parity.py to include new manifest entries for P4. - Enhanced test_script_tools.py to include checks for APU primitives filelists. - Added assertions for APU primitives in the formal filelists test to ensure proper scoping and inclusion.
88 lines
3.0 KiB
Systemverilog
88 lines
3.0 KiB
Systemverilog
// Copyright (c) 2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
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// SPDX-License-Identifier: MulanPSL-2.0
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module apu_primitives_formal;
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(* anyseq *) (* gclk *) reg clk_i;
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wire rst_n_i, f_past_valid;
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wire [2:0] scenario_o, phase_o;
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wire request_valid_o, request_ready_o, request_accept_o;
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wire [3:0] request_class_o;
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wire kernel_busy_o, kernel_outstanding_o;
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wire [31:0] kernel_latency_o;
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wire result_valid_o, result_kernel_o, result_error_o;
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wire [ 5:0] result_error_code_o;
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wire [ 3:0] result_error_stage_o;
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wire [ 7:0] result_error_reason_o;
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wire [31:0] result_cycles_o;
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wire done_o, last_error_o;
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wire [ 5:0] last_error_code_o;
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wire [ 3:0] last_error_stage_o;
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wire [ 7:0] last_error_reason_o;
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wire [31:0] last_data_o;
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wire [6:0] input_count_o, output_count_o;
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wire memory_request_o;
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apu_primitives_formal_design u_design (.*);
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always @(posedge clk_i) begin
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assume (scenario_o <= 3'd6);
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if (rst_n_i) begin
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assert (input_count_o <= 7'd64);
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assert (output_count_o <= 7'd64);
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if (kernel_busy_o && request_valid_o && (request_class_o != 4'd5)) begin
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assert (!request_ready_o);
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end
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if (request_accept_o && (request_class_o != 4'd5)) begin
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assert (!kernel_busy_o);
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end
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if (result_valid_o && result_kernel_o && !result_error_o) begin
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assert (kernel_outstanding_o);
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assert (kernel_latency_o <= result_cycles_o);
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end
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if (done_o && (scenario_o == 3'd0)) begin
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assert (last_error_o);
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assert ({last_error_code_o, last_error_stage_o, last_error_reason_o} ==
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{6'd11, 4'd11, 8'd5});
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end
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if (done_o && (scenario_o == 3'd1)) begin
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assert (!last_error_o);
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assert (last_data_o == 32'hdead_beef);
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end
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if (done_o && (scenario_o == 3'd2)) begin
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assert (!last_error_o);
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assert (last_data_o == 32'h1357_9bdf);
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end
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if (done_o && (scenario_o == 3'd3)) begin
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assert (!last_error_o);
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assert (last_data_o == 32'h2468_ace0);
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end
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if (done_o && (scenario_o == 3'd4)) begin
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assert (last_error_o);
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assert ({last_error_code_o, last_error_stage_o, last_error_reason_o} ==
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{6'd11, 4'd11, 8'd5});
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end
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if (done_o && (scenario_o == 3'd5)) begin
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assert (!last_error_o);
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assert (output_count_o == 7'd1);
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end
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if ((scenario_o == 3'd6) && (phase_o == 3'd1)) begin
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assert (!memory_request_o);
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end
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if (done_o && (scenario_o == 3'd6)) begin
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assert (last_error_o);
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assert ({last_error_code_o, last_error_stage_o, last_error_reason_o} ==
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{6'd11, 4'd11, 8'd5});
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assert (last_data_o == 32'd0);
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end
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end
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cover (rst_n_i && done_o);
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cover (rst_n_i && ((scenario_o != 3'd2) ||
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(kernel_outstanding_o && request_valid_o && !request_ready_o &&
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(request_class_o == 4'd4))));
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end
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logic s_unused;
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assign s_unused = f_past_valid ^ phase_o[0];
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endmodule
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