mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-06 14:55:14 +00:00
maksyuki
57ffd03216
- Modified test_apu_register_parity.py to reflect changes in P4 ISA definitions. - Updated test_apu_register_parity.py to include new manifest entries for P4. - Enhanced test_script_tools.py to include checks for APU primitives filelists. - Added assertions for APU primitives in the formal filelists test to ensure proper scoping and inclusion.
381 lines
16 KiB
Systemverilog
381 lines
16 KiB
Systemverilog
// Copyright (c) 2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
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// SPDX-License-Identifier: MulanPSL-2.0
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`include "apu_define.svh"
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module apu_p4_sequencer_tb;
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logic clk_i = 1'b0;
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logic rst_n_i = 1'b0;
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logic soft_reset_i, resource_reset_i, abort_i, counter_clear_i, launch_i;
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logic store_loader_active, store_loader_write;
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logic [10:0] store_loader_addr;
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logic [63:0] store_loader_data, store_loader_read_data;
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logic store_loader_valid;
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logic fetch, fetch_valid;
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logic [10:0] fetch_addr;
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logic [63:0] fetch_data;
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logic [2:0][10:0] entry_pc, entry_first, entry_last;
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logic [2:0][15:0] entry_max_loop;
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logic [2:0][23:0] entry_max_retired;
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logic [2:0][16:0] entry_scratch_base, entry_scratch_bytes;
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logic [2:0][31:0] entry_primitive_mask;
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logic [2:0][15:0] entry_table_offset, entry_table_bytes;
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logic primitive_req_valid, primitive_req_ready, primitive_result_valid;
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logic [63:0] primitive_instruction;
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logic [31:0] primitive_source0, primitive_source1, primitive_destination;
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logic [3:0] primitive_result_dst;
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logic [3:0][31:0] primitive_result_data;
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logic [2:0] primitive_result_words;
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logic primitive_result_kernel, primitive_error, primitive_kernel_done, primitive_busy;
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logic [5:0] primitive_error_code;
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logic [3:0] primitive_error_stage;
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logic [7:0] primitive_error_reason;
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logic primitive_input_exhausted, primitive_input_ready, primitive_output_ready;
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logic memory_req, memory_write, memory_valid, memory_error;
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logic [16:0] memory_addr;
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logic [31:0] memory_write_data, memory_read_data;
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logic [3:0] memory_strb;
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logic inject_active, inject_req, inject_write;
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logic [16:0] inject_addr;
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logic [31:0] inject_data;
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logic [ 3:0] inject_strb;
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logic codec_req, codec_write;
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logic [16:0] codec_addr;
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logic [31:0] codec_data;
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logic [ 3:0] codec_strb;
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logic [31:0] status, retired;
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logic [15:0][31:0] gpr;
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logic trapped, trap_event, abort_done, fault_valid, sequencer_idle;
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logic [5:0] fault_code;
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logic [3:0] fault_stage;
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logic [1:0] fault_resp;
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logic [7:0] fault_index;
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logic [31:0] fault_addr, fault_detail;
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logic [63:0] perf_retired;
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logic [16:0] active_scratch_base, active_scratch_bytes;
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logic [31:0] active_primitive_mask;
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logic [15:0] active_table_offset, active_table_bytes;
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logic launch_epoch;
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always #5 clk_i = ~clk_i;
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always_ff @(posedge clk_i) begin
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if (rst_n_i && primitive_busy && primitive_req_valid &&
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(primitive_instruction[63:60] != `APB4_APU__MC_CLASS_KERNEL)) begin
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$fatal(1, "APU-P4 issued a second primitive while the kernel owned local SRAM");
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end
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end
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assign codec_req = inject_active ? inject_req : memory_req;
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assign codec_write = inject_active ? inject_write : memory_write;
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assign codec_addr = inject_active ? inject_addr : memory_addr;
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assign codec_data = inject_active ? inject_data : memory_write_data;
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assign codec_strb = inject_active ? inject_strb : memory_strb;
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apu_control_store u_control_store (
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.clk_i (clk_i),
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.rst_n_i (rst_n_i),
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.loader_active_i(store_loader_active),
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.loader_read_i (1'b0),
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.loader_write_i (store_loader_write),
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.loader_addr_i (store_loader_addr),
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.loader_data_i (store_loader_data),
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.loader_data_o (store_loader_read_data),
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.loader_valid_o (store_loader_valid),
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.image_valid_i (1'b1),
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.fetch_i (fetch),
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.fetch_addr_i (fetch_addr),
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.fetch_data_o (fetch_data),
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.fetch_valid_o (fetch_valid)
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);
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apu_local_sram u_local_sram (
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.clk_i (clk_i),
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.rst_n_i (rst_n_i),
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.image_valid_i (1'b1),
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.table_bytes_i (16'd0),
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.epoch_clear_i (launch_epoch || soft_reset_i || resource_reset_i || abort_i),
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.loader_active_i (1'b0),
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.loader_req_i (1'b0),
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.loader_addr_i (17'd0),
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.loader_data_i (32'd0),
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.loader_strb_i (4'd0),
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.loader_ready_o (),
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.codec_req_i (codec_req),
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.codec_write_i (codec_write),
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.codec_addr_i (codec_addr),
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.codec_data_i (codec_data),
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.codec_strb_i (codec_strb),
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.codec_ready_o (),
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.codec_data_o (memory_read_data),
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.codec_valid_o (memory_valid),
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.codec_access_err_o(memory_error)
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);
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apu_primitive_dispatcher u_dispatcher (
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.clk_i (clk_i),
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.rst_n_i (rst_n_i),
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.flush_i (launch_epoch || soft_reset_i || resource_reset_i || abort_i),
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.req_valid_i (primitive_req_valid),
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.req_ready_o (primitive_req_ready),
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.instruction_i (primitive_instruction),
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.source0_i (primitive_source0),
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.source1_i (primitive_source1),
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.destination_i (primitive_destination),
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.scratch_base_i (active_scratch_base),
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.scratch_bytes_i (active_scratch_bytes),
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.table_offset_i (active_table_offset),
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.table_bytes_i (active_table_bytes),
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.result_valid_o (primitive_result_valid),
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.result_dst_o (primitive_result_dst),
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.result_data_o (primitive_result_data),
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.result_words_o (primitive_result_words),
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.result_kernel_o (primitive_result_kernel),
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.error_o (primitive_error),
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.error_code_o (primitive_error_code),
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.error_stage_o (primitive_error_stage),
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.error_reason_o (primitive_error_reason),
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.cycles_o (),
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.kernel_done_o (primitive_kernel_done),
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.busy_o (primitive_busy),
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.input_exhausted_o(primitive_input_exhausted),
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.input_ready_o (primitive_input_ready),
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.output_ready_o (primitive_output_ready),
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.input_count_o (),
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.output_count_o (),
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.kernel_busy_o (),
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.memory_req_o (memory_req),
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.memory_write_o (memory_write),
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.memory_addr_o (memory_addr),
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.memory_data_o (memory_write_data),
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.memory_strb_o (memory_strb),
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.memory_valid_i (memory_valid),
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.memory_data_i (memory_read_data),
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.memory_error_i (memory_error),
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.input_valid_i (1'b0),
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.input_data_i (41'd0),
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.input_accept_o (),
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.output_valid_o (),
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.output_data_o (),
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.output_accept_i (1'b0)
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);
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apu_codec_sequencer #(
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.EnableP4(1'b1)
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) u_sequencer (
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.clk_i (clk_i),
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.rst_n_i (rst_n_i),
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.soft_reset_i (soft_reset_i),
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.resource_reset_i (resource_reset_i),
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.counter_clear_i (counter_clear_i),
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.abort_i (abort_i),
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.launch_i (launch_i),
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.launch_entry_i (2'd0),
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.image_valid_i (1'b1),
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.timeout_i (32'd4096),
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.entry_pc_i (entry_pc),
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.entry_first_i (entry_first),
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.entry_last_i (entry_last),
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.entry_max_loop_i (entry_max_loop),
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.entry_max_retired_i (entry_max_retired),
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.entry_scratch_base_i (entry_scratch_base),
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.entry_scratch_bytes_i (entry_scratch_bytes),
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.entry_primitive_mask_i (entry_primitive_mask),
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.entry_table_offset_i (entry_table_offset),
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.entry_table_bytes_i (entry_table_bytes),
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.input_exhausted_i (primitive_input_exhausted),
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.input_ready_i (primitive_input_ready),
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.output_ready_i (primitive_output_ready),
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.kernel_done_i (primitive_kernel_done),
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.transport_idle_success_i (1'b1),
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.stall_i (1'b0),
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.cause_valid_i (1'b0),
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.cause_code_i (6'd0),
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.cause_stage_i (4'd0),
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.cause_resp_i (2'd0),
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.cause_index_i (8'd0),
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.cause_addr_i (32'd0),
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.cause_detail_i (32'd0),
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.primitive_req_valid_o (primitive_req_valid),
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.primitive_req_ready_i (primitive_req_ready),
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.primitive_instruction_o (primitive_instruction),
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.primitive_source0_o (primitive_source0),
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.primitive_source1_o (primitive_source1),
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.primitive_destination_o (primitive_destination),
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.primitive_result_valid_i (primitive_result_valid),
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.primitive_result_dst_i (primitive_result_dst),
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.primitive_result_data_i (primitive_result_data),
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.primitive_result_words_i (primitive_result_words),
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.primitive_result_kernel_i(primitive_result_kernel),
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.primitive_error_i (primitive_error),
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.primitive_error_code_i (primitive_error_code),
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.primitive_error_stage_i (primitive_error_stage),
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.primitive_error_reason_i (primitive_error_reason),
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.fetch_o (fetch),
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.fetch_addr_o (fetch_addr),
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.fetch_data_i (fetch_data),
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.fetch_valid_i (fetch_valid),
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.stat_o (status),
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.retired_o (retired),
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.gpr_o (gpr),
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.trapped_o (trapped),
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.trap_event_o (trap_event),
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.abort_done_o (abort_done),
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.fault_valid_o (fault_valid),
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.fault_code_o (fault_code),
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.fault_stage_o (fault_stage),
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.fault_resp_o (fault_resp),
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.fault_index_o (fault_index),
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.fault_addr_o (fault_addr),
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.fault_detail_o (fault_detail),
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.perf_retired_o (perf_retired),
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.active_scratch_base_o (active_scratch_base),
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.active_scratch_bytes_o (active_scratch_bytes),
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.active_primitive_mask_o (active_primitive_mask),
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.active_table_offset_o (active_table_offset),
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.active_table_bytes_o (active_table_bytes),
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.launch_epoch_o (launch_epoch),
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.idle_o (sequencer_idle)
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);
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function automatic logic [63:0] encode_instruction(
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input logic [3:0] instruction_class_i, input logic [3:0] opcode_i, input logic [3:0] dst_i,
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input logic [3:0] src0_i, input logic [3:0] src1_i, input logic [7:0] aux_i,
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input logic [31:0] immediate_i);
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return {instruction_class_i, opcode_i, 4'd0, dst_i, src0_i, src1_i, aux_i, immediate_i};
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endfunction
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task automatic load_instruction(input logic [10:0] address_i, input logic [63:0] data_i);
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begin
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@(negedge clk_i);
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store_loader_active = 1'b1;
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store_loader_write = 1'b1;
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store_loader_addr = address_i;
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store_loader_data = data_i;
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@(negedge clk_i);
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store_loader_write = 1'b0;
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end
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endtask
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task automatic inject_word(input logic [16:0] address_i, input logic [31:0] data_i);
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begin
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@(negedge clk_i);
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inject_active = 1'b1;
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inject_req = 1'b1;
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inject_write = 1'b1;
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inject_addr = address_i;
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inject_data = data_i;
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inject_strb = 4'hf;
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@(negedge clk_i);
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inject_active = 1'b0;
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inject_req = 1'b0;
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inject_write = 1'b0;
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end
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endtask
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initial begin
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soft_reset_i = 1'b0;
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resource_reset_i = 1'b0;
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abort_i = 1'b0;
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counter_clear_i = 1'b0;
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launch_i = 1'b0;
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store_loader_active = 1'b0;
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store_loader_write = 1'b0;
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store_loader_addr = 11'd0;
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store_loader_data = 64'd0;
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inject_active = 1'b0;
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inject_req = 1'b0;
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inject_write = 1'b0;
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inject_addr = 17'd0;
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inject_data = 32'd0;
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inject_strb = 4'd0;
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entry_pc = {11'd0, 11'd0, 11'd0};
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entry_first = {11'd0, 11'd0, 11'd0};
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entry_last = {11'd10, 11'd10, 11'd10};
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entry_max_loop = {16'd4, 16'd4, 16'd4};
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entry_max_retired = {24'd32, 24'd32, 24'd32};
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entry_scratch_base = {17'd0, 17'd0, 17'd0};
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entry_scratch_bytes = {17'h06000, 17'h06000, 17'h06000};
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entry_primitive_mask = {32'h0000_0070, 32'h0000_0070, 32'h0000_0070};
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entry_table_offset = {16'd0, 16'd0, 16'd0};
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entry_table_bytes = {16'd0, 16'd0, 16'd0};
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rst_n_i = 1'b0;
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repeat (3) @(posedge clk_i);
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rst_n_i = 1'b1;
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repeat (2) @(posedge clk_i);
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load_instruction(11'd0, encode_instruction(4'd1, 4'd1, 4'd0, 4'd0, 4'd0, 8'd0, 32'h0000_0100));
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load_instruction(11'd1, encode_instruction(4'd1, 4'd1, 4'd1, 4'd0, 4'd0, 8'd0, 32'h0000_0180));
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load_instruction(11'd2, encode_instruction(4'd1, 4'd1, 4'd4, 4'd0, 4'd0, 8'd0, 32'h0000_01c0));
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load_instruction(11'd3, encode_instruction(4'd1, 4'd1, 4'd5, 4'd0, 4'd0, 8'd0, 32'h0000_0200));
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load_instruction(11'd4, encode_instruction(4'd1, 4'd1, 4'd6, 4'd0, 4'd0, 8'd0, 32'h1234_5678));
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load_instruction(11'd5, encode_instruction(4'd5, 4'd0, 4'd4, 4'd0, 4'd1, 8'h80, 32'd1));
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load_instruction(11'd6, encode_instruction(4'd1, 4'd1, 4'd7, 4'd0, 4'd0, 8'd0, 32'h0000_0055));
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load_instruction(11'd7, encode_instruction(4'd4, 4'd1, 4'd0, 4'd5, 4'd6, 8'd0, 32'd0));
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load_instruction(11'd8, encode_instruction(4'd0, 4'd8, 4'd0, 4'd0, 4'd0, 8'd1, 32'd0));
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load_instruction(11'd9, encode_instruction(4'd4, 4'd0, 4'd3, 4'd5, 4'd0, 8'd0, 32'd0));
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load_instruction(11'd10, encode_instruction(4'd0, 4'd1, 4'd0, 4'd0, 4'd0, 8'd0, 32'd0));
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@(negedge clk_i);
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launch_i = 1'b1;
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@(negedge clk_i);
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launch_i = 1'b0;
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store_loader_active = 1'b0;
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inject_word(17'h00100, 32'd1000);
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inject_word(17'h00140, 32'h4000_0000);
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inject_word(17'h00180, 32'h0000_0140);
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for (int cycle = 0; cycle < 10000; cycle++) begin
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@(posedge clk_i);
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if (fault_valid || trapped) begin
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$fatal(
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1,
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"APU-P4 sequencer fault code=%0d detail=%08x status=%08x insn=%016x legal=%0d r5=%08x r6=%08x valid=%0d",
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fault_code, fault_detail, status, u_sequencer.s_instruction_q,
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apu_microcode_pkg::instruction_encoding_valid(u_sequencer.s_instruction_q), gpr[5],
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gpr[6], u_local_sram.s_mutable_valid_q[17'h00200>>2]);
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end
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if (sequencer_idle && !primitive_busy && (retired != 32'd0)) break;
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if (cycle == 9999) $fatal(1, "APU-P4 sequencer timed out");
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end
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if ((gpr[3] != 32'h1234_5678) || (gpr[4] != 32'd1) || (gpr[7] != 32'h55) ||
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(retired != 32'd11) || (perf_retired != 64'd11)) begin
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$fatal(1, "APU-P4 sequencer mismatch r3=%0d r4=%0d r7=%0d retired=%0d perf=%0d", gpr[3],
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gpr[4], gpr[7], retired, perf_retired);
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end
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@(negedge clk_i);
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store_loader_active = 1'b1;
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launch_i = 1'b1;
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@(negedge clk_i);
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launch_i = 1'b0;
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store_loader_active = 1'b0;
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@(posedge clk_i);
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if (u_local_sram.s_mutable_valid_q[17'h00200>>2] ||
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u_dispatcher.u_kernel_engine.s_resample_profile_valid_q) begin
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$fatal(1, "APU-P4 launch did not clear the mutable-data epoch");
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end
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inject_word(17'h00100, 32'd2000);
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inject_word(17'h00140, 32'h4000_0000);
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inject_word(17'h00180, 32'h0000_0140);
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for (int cycle = 0; cycle < 10000; cycle++) begin
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@(posedge clk_i);
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if (fault_valid || trapped) begin
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$fatal(1, "APU-P4 second launch fault code=%0d detail=%08x", fault_code, fault_detail);
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end
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if (sequencer_idle && !primitive_busy && (retired != 32'd0)) break;
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if (cycle == 9999) $fatal(1, "APU-P4 second launch timed out");
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end
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if ((gpr[3] != 32'h1234_5678) || (gpr[4] != 32'd1) || (retired != 32'd11)) begin
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$fatal(1, "APU-P4 second launch result mismatch");
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end
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$display("APU_P4_SEQUENCER_PASS");
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$finish;
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end
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logic s_unused;
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assign s_unused = store_loader_read_data[0] ^ store_loader_valid ^ trap_event ^ abort_done ^
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fault_stage[0] ^ fault_resp[0] ^ fault_index[0] ^ fault_addr[0] ^
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active_primitive_mask[0];
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endmodule
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