mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-05 06:32:37 +00:00
maksyuki
269edc43a6
The C906 resets with caches and the BPU disabled (mhcr=0) and does not initialize the cache/predictor RAMs (aq_cp0_ext_csr.v). The upstream reference crt0 (openc906 smart_run/tests/lib/crt0.s) invalidates them via mcor before enabling mhcr; skipping mcor makes the core execute through uninitialized predictor/cache state (wild control flow with no trap), and leaving caches off makes SDRAM execution ~100x slower, which livelocked the RT-Thread 1 kHz tick ISR before the first selftest marker. Apply the upstream sequence at the earliest point of both HP boot paths: RT-Thread start.S and the OpenSBI platform early_init. MMIO windows stay strong-order non-cacheable via the sysmap override, so enabling the D-cache is safe. hp-rtthread-sim now passes with all selftest markers (6,373,952 cycles in 542 s).
78 lines
1.8 KiB
ArmAsm
78 lines
1.8 KiB
ArmAsm
.section .text.start
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.global _start
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_start:
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csrw mie, zero
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csrw satp, zero
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li t0, 0x6000
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csrw mstatus, t0
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# C906 resets with caches and the BPU disabled (mhcr=0) and does not
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# initialize the cache/predictor RAMs; the upstream reference crt0
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# (smart_run/tests/lib/crt0.s) invalidates them via mcor before enabling
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# mhcr, otherwise the core fetches/stores through stale state.
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li t0, 0x30013
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csrs 0x7c2, t0 # mcor: invalidate BTB/BHT/D-cache/I-cache
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li t0, 0x7f
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csrs 0x7c1, t0 # mhcr: IE|DE|WA|RSE|BPE|BTBE
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# Uncached SDRAM execution is ~100x slower otherwise, and the 1 kHz tick
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# ISR round-trip then exceeds the tick period (livelock). MMIO windows
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# stay strong-order non-cacheable via the sysmap override.
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.option push
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.option norelax
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la gp, __global_pointer$
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.option pop
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la sp, __rt_rvstack
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la t0, __bss_start
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la t1, __bss_end
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1:
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bgeu t0, t1, 2f
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sd zero, 0(t0)
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addi t0, t0, 8
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j 1b
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2:
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la t0, trap_entry
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csrw mtvec, t0
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csrw mscratch, sp
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call rs_rtt_start
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3:
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wfi
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j 3b
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.section .text
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.global rs_rtt_context_probe
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rs_rtt_context_probe:
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addi sp, sp, -48
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sd ra, 0(sp)
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sd s0, 8(sp)
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sd s1, 16(sp)
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sd s2, 24(sp)
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sd s3, 32(sp)
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sd a0, 40(sp)
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mv s0, a0
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mv s2, a0
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not s3, a0
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li s1, 8
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1:
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li a0, 1
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call rt_thread_delay
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# Compare against memory, so identical truncation of saved registers cannot
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# accidentally satisfy a register-to-register comparison.
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ld t1, 40(sp)
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bne s0, t1, 2f
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bne s2, t1, 2f
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not t0, t1
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bne t0, s3, 2f
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addi s1, s1, -1
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bnez s1, 1b
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li a0, 0
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j 3f
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2:
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li a0, 1
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3:
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ld ra, 0(sp)
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ld s0, 8(sp)
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ld s1, 16(sp)
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ld s2, 24(sp)
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ld s3, 32(sp)
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addi sp, sp, 48
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ret
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