mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-04 22:32:36 +00:00
maksyuki
8d735aafbd
- Adjusted slot assignments in to reflect new peripheral mappings. - Updated to validate new OpenC906 configurations, including generator and profile checks. - Modified to reference the new Std-series VexiiRiscv generator. - Changed cache maintenance instructions in to align with C906 specifications. - Revised assertions in to account for internal unit removals. - Updated to reflect changes in peripheral interface counts and policies. - Added new test file to ensure preservation of the frozen HP configuration in the Std-series generator.
41 lines
1.6 KiB
Typst
41 lines
1.6 KiB
Typst
#import "../style.typ": *
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#import "../ip-reference.typ": inline, subhead
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#import "../diagram-packages.typ": circuit-diagram
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#pagebreak(weak:true)
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#context metadata((kind:"ip-start",id:"hp-plic",page:here().page()))
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===== HP Platform-Level Interrupt Controller (PLIC) <hp-plic>
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#let chapter=data.chapters.at("plic")
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#let r=data.regions.find(r=>r.symbol=="HP_C906_SYS")
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The HP external interrupt controller is *internal to the OpenC906 core*: the core BIU decodes
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the T-Head c900 PLIC layout at the base of the reserved system window at #code(r.base_hex)
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(size #r.size_label), which never appears as a SoC fabric target. This chapter therefore has
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*no SoC register table*; register-bit detail follows the T-Head C906 manuals, which remain
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outside this publication's scope together with the CPU ISA/CSR manuals.
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#subhead("hp-plic","Features and Block Diagram",5)
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#list(..chapter.at("features",default:()).map(inline))
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#block(breakable:false)[
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#figure(circuit-diagram("hp-plic"),kind:image,supplement:[Figure],caption:[#chapter.title integration boundary.])
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#label("circuit-hp-plic")
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]
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#subhead("hp-plic","Functional Description",5)
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#for paragraph in chapter.notes { par(inline(paragraph)) }
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#subhead("hp-plic","Software",5)
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#enum(..chapter.software_steps.map(inline))
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#block(breakable:false)[
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#set text(size:9pt)
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#source("rtl/mini/top/hp_core_wrapper.sv",title:"Source wiring into the core") ·
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#source("rtl/mini/top/apb4_periph.sv",title:"SoC external source assignments") ·
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#source("app/ports/linux/linux/retrosoc_hp.dts",title:"thead,c900-plic declaration")
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]
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#context metadata((kind:"ip-end",id:"hp-plic",page:here().page()))
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