mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-04 22:32:36 +00:00
maksyuki
8d735aafbd
- Adjusted slot assignments in to reflect new peripheral mappings. - Updated to validate new OpenC906 configurations, including generator and profile checks. - Modified to reference the new Std-series VexiiRiscv generator. - Changed cache maintenance instructions in to align with C906 specifications. - Revised assertions in to account for internal unit removals. - Updated to reflect changes in peripheral interface counts and policies. - Added new test file to ensure preservation of the frozen HP configuration in the Std-series generator.
185 lines
10 KiB
Typst
185 lines
10 KiB
Typst
#import "../style.typ": *
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#change-start("v05-emphasis-architecture","Selected body emphasis: architecture")
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#import "../figures.typ": *
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#import "../waveforms.typ": timing
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#import "../diagram-packages.typ": memory-window-diagram
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#import "../soc-architecture.typ": soc-functional-diagram
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= System Architecture
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#change-start("dev-architecture","Ten-master fabric, address map, LP IRQ and lifecycle reference")
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== Introduction
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=== SoC Architecture
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Mini PRODUCT contains *two fixed harts*, an LP-owned control plane, a native HP data fabric and
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two APB4 register islands. There is *no hardware cache coherency*. Software transfers shared
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buffer ownership explicitly and performs the required fences and cache maintenance.
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#figure(soc-functional-diagram(), caption:[Mini PRODUCT functional architecture and clock domains.])<soc-functional-overview>
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=== Management Processor
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==== Hazard3
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Hazard3 is hart 0 and the *root-management processor*. The reference profile selects RV32IM
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firmware. Its AHB-Lite interface is adapted to AXI32 for control access; memory transactions
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are directed through the LP gateway to the shared data plane. The management JTAG path provides
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halt, resume, register and system-bus access. LP retains control while HP is held in reset.
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#source-note("docs/hazard3-debug.md", title:"Management debug transport and acceptance flow")
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=== Application Processor
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==== OpenC906
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The HP hart is the locked T-Head OpenC906 pre-generated RTL in its default RV64GC
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configuration, with supervisor/user modes and Sv39 virtual memory. Hart 1 issues a single
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*128-bit AXI4 master*, downsized to the 64-bit HP data fabric and split into memory and MMIO
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ports by address window. The uncached MMIO path is downsized further and crosses into the LP
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control plane. Its CLINT/PLIC are *core-internal* (c900 layouts) and never appear as SoC
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fabric targets. OpenSBI/Linux inputs and the vendored core revision are dependency-locked.
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#source-note("docs/lp-hp-architecture.md", title:"LP/HP architecture and boot contract")
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#include "processor-details.typ"
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== Interconnect
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=== AXI4 and APB4 Interfaces
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The product replaces the former NMI/AXI4-Lite/APB3 organization with AXI4 control and data
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paths and APB4 register targets. The compatibility RIBP boundary for selected MPW cores is
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described in @mpw. It is not the PRODUCT data fabric.
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The LP control fabric uses 32-bit data. APB accesses cross LP to PCLK through asynchronous
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request/response bridges. The HP data plane uses 64-bit data, 32-bit addresses and seven-bit
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global transaction IDs. Adapters preserve byte lanes and response attribution across width
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and clock boundaries. HP MMIO cannot write root-owned SYSCTRL/RCU, watchdog, GPIO administration
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and other protected management controls.
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#change-start("system-fabric", "PRODUCT control and memory circuit paths")
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#figure(fabric-diagram(), caption:[PRODUCT control and memory paths. Gateway adaptation and CDC separate the functional clock domains.])<fabric-diagram>
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#change-end("system-fabric")
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=== Common Bus Protocols <common-protocols>
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The following WaveDrom examples define the handshake notation used by the IP chapters.
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They show valid protocol ordering, not guaranteed transaction latency. Address windows,
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byte strobes, burst limits, access permissions and IP-specific side effects remain binding.
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#timing("apb4",[APB4 setup, access and wait-state example.])
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#timing("axi4",[AXI4 read-address and response-channel example.])
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#timing("axis",[AXI4-Stream backpressure and end-of-transfer example.])
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=== Interconnect Matrix
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The #data.policies.len() initiator identities access #data.targets.len() memory targets. The crossbar arbitrates reads and
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writes separately for each target. I/O gateway A combines USB2, SDIO0 and the APU private
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master; gateway B combines SDIO1 and SPI-SD. JPEG occupies slot 6, EXT-H slot 7,
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GA2D slot 8 and NPU slot 9.
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#note[The matrix on the next page is generated from the RTL access policy. R/W permission is
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subject to active memory-pad mode, resource ownership, target readiness and EXT-H address bounds.
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An allowed entry does not guarantee throughput.]
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#pagebreak()
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#figure(matrix-diagram(), caption:[AXI64 memory access matrix: R = read, W = write, - = denied.])<bus-matrix>
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The HP memory master is the only instruction-permitted initiator. HP cache attributes are preserved;
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DMA, I/O gateways, LP gateway, JPEG, EXT-H, GA2D and NPU require non-cacheable transactions. XPI is read-only
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on this data plane; indirect writes use its APB-controlled command engine.
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Denied accesses return a finite error response with source attribution. EXT-H has additional
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read/write address bounds. SRAM and SDRAM use multiple outstanding credits; serial targets
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have more restricted concurrency. Software must not assume coherency or treat theoretical bus
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width multiplied by clock rate as measured application bandwidth.
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#source-note("rtl/mini/integration/soc_topology.json", title:"Generated matrix source: data_master_policies")
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#pagebreak()
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#include "bus-programming.typ"
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=== Address Mapping
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All ranges below are inclusive. The SRAM range is resolved using the reference profile's
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32 KiB setting. Peripheral windows are address allocations; not every offset implements a
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register. Detailed contracts define valid offsets and access modes. Reserved regions do not
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advertise an implemented IP.
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#ds-table("memory", [Memory and reserved data apertures],
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([Window], [Base], [End], [Size]),
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data.regions.filter(r=>r.route in ("axi4","ram","reserved") and r.size > 4096).map(r=>(
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code(r.symbol),code(r.base_hex),code(r.end_hex),r.size_label)),
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widths:(1fr,1.1fr,1.1fr,0.65fr),
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notes:[FLASH is the reset/boot alias. SPISD's former card-data aperture is reserved. HP_C906_SYS
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is reserved for the HP core's internal CLINT/PLIC decode; it is not a SoC fabric target. The physical
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capacity of fitted XPI/OPI devices remains board-dependent.],
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)
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#ds-table("registers", [Register and interrupt-controller windows],
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([Window], [Base], [Size], [Integration]),
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data.regions.filter(r=>not(r.route in ("axi4","ram","reserved") and r.size > 4096)).map(r=>(
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code(r.symbol),code(r.base_hex),r.size_label,r.availability)),
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widths:(1.3fr,1fr,0.6fr,1.35fr),
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)
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<reserved>
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GA2D occupies the active 4 KiB APB4 window at 0x10012000. The former SPI-SD data aperture
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remains reserved. PRODUCT keeps a compatibility responder at the former selectable user-IP
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window; it does not instantiate MPW user IPs there.
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#block(breakable:false)[
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#figure(memory-window-diagram(),kind:image,supplement:[Figure],caption:[Selected PRODUCT memory address windows in the reference configuration.])<memory-window-layout>
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]
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#pagebreak()
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#include "memory-use.typ"
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== Clock and Reset
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=== Architecture
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The RCU compatibility wrapper contains the product clock/reset subsystem. AON uses REF24;
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LP resets to REF24 and HP resets to the external 72 MHz safe source. The reference profile
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disables the PLL. Generic PLL selectors model 72-240 MHz in 24 MHz steps; these are digital
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integration choices, not qualified silicon speed grades.
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#change-start("system-clocks", "System clock and reset circuit organization")
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#figure(clock-diagram(), caption:[Clock-domain organization and reset defaults. Frequencies shown are configuration values.])<clock-diagram>
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#change-end("system-clocks")
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The memory root is the stable external 72 MHz clock divided by two. Audio, DVP pixel, ULPI and
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JTAG have independent clocks. The inventory below lists domains without presenting synthesis
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constraint periods as measured operating limits.
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#ds-table("domains", [Canonical clock/reset-domain inventory],
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([Domain], [Clock signal], [Reset signal]),
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data.clocks.map(d=>(d.name,code(d.clock),code(d.reset))),widths:(0.6fr,1.45fr,1.45fr),
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)
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=== Reset and Logic
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Clock changes validate the request, block new traffic, quiesce and drain accepted work, park
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LP, select the safe source, apply and qualify the PLL setting, then restore the requested
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roots. Timeout or lock loss returns to the safe source and retains fault status. Reset
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release uses per-domain synchronizers; coordinated warm flushes prevent stale transactions
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from re-entering a restarted domain.
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#source-note("docs/pll-clock-control.md", title:"Clock transition, fault and PLL control contract")
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#tbd[PLL jitter, PVT range, clock-tree closure and pad-level reset timing require physical
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qualification. No crystal-oscillator range or maximum core frequency is specified here.]
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#include "operating-states.typ"
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#include "reset-summary.typ"
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#include "clock-programming.typ"
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== Interrupt System
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The management interrupt vector is 64 bits wide; two local causes and 62 external positions
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are distinct from the currently allocated source list. The following numbers are
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LP vector bits, not HP PLIC IDs. Peripheral-level status registers identify causes
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within an aggregate source. Resource-controlled interrupts are routed according to ownership.
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#ds-table("lp-irqs", [LP interrupt vector],
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([LP bit], [Source], [Description]),
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data.interrupts.map(i=>(str(i.core_bit),code(i.name),i.description)),
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widths:(0.45fr,1.25fr,2fr),
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)
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HP local software/timer interrupts come from the core-internal CLINT, and external sources
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from the core-internal PLIC (T-Head c900 layouts, decoded inside the OpenC906 core). Sixteen
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SoC external sources are wired; *SoC source n reaches software as PLIC ID n+16*. Source 1 is
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UART1, source 2 is the mailbox doorbell, source 3 is EXT-H, and sources 4-12 are the
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resource-owned DMA, USB2, SDIO0, SDIO1, SPI-SD, JPEG, APU, GA2D and NPU lines; sources 13-15
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are reserved. GA2D uses LP vector bit 32 (external ordinal 30),
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which is distinct from HP external source 11; NPU uses LP vector bit 33 (external ordinal 31)
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or HP external source 12 according to Resource Controller ownership. The PLIC drives the
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hart's machine and supervisor external interrupts.
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Claim/complete and priority rules follow the T-Head C906 manuals.
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#block(above:rhythm.metadata-before,below:rhythm.metadata-after,breakable:false)[
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#set text(size:9pt)
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#source("docs/ip/hp-platform.md",title:"HP PLIC, local interrupts and mailbox") · LP software: @irq-runtime
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]
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#include "system-management.typ"
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#include "register-programming.typ"
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#include "interface-subsets.typ"
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#change-end("dev-architecture")
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#change-end("v05-emphasis-architecture")
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