mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-04 22:32:36 +00:00
maksyuki
8d735aafbd
- Adjusted slot assignments in to reflect new peripheral mappings. - Updated to validate new OpenC906 configurations, including generator and profile checks. - Modified to reference the new Std-series VexiiRiscv generator. - Changed cache maintenance instructions in to align with C906 specifications. - Revised assertions in to account for internal unit removals. - Updated to reflect changes in peripheral interface counts and policies. - Added new test file to ensure preservation of the frozen HP configuration in the Std-series generator.
241 lines
14 KiB
Python
241 lines
14 KiB
Python
"""Source-bound data for representative field, instruction, memory and circuit diagrams."""
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from __future__ import annotations
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import copy
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import importlib.util
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import json
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import re
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import sys
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from pathlib import Path
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from publications.implementation_reference import without_comments
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from publications.register_reference import number
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from publications.circuit_reference import validate_instance_connections
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from publications.instruction_reference import instruction_families
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from publications.format_reference import collect_layouts
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from publications.storage_reference import collect_storage
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from publications.soc_diagram_reference import collect_soc_diagram
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def dependencies(spec: dict) -> set[str]:
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paths = set(spec.get("sources", []))
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if spec.get("soc_architecture_catalog"):
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paths.add(spec["soc_architecture_catalog"])
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for binding in spec.get("bindings", []):
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paths.add(binding["file"])
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for circuit in spec.get("circuits", {}).values():
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for node in circuit["nodes"]:
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paths.update(node.get("sources", []))
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for edge in circuit["edges"]:
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paths.update(binding["file"] for binding in edge["bindings"])
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return paths
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def validate_bindings(root: Path, bindings: list[dict]) -> None:
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for binding in bindings:
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source = (root / binding["file"]).read_text(encoding="utf-8")
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if re.sub(r"\s+", "", without_comments(binding["text"])) not in re.sub(r"\s+", "", without_comments(source)):
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raise ValueError(f"diagram source binding changed: {binding['file']}")
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def validate_fields(fields: list[dict], total_bits: int) -> None:
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occupied, names = set(), set()
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for field in fields:
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name, lsb, bits = field["name"], field["lsb"], field["bits"]
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if name in names or type(lsb) is not int or type(bits) is not int or lsb < 0 or bits < 1:
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raise ValueError("invalid or duplicate diagram field")
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positions = set(range(lsb, lsb + bits))
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if occupied & positions or max(positions) >= total_bits:
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raise ValueError("diagram fields overlap or exceed the layout")
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names.add(name)
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occupied.update(positions)
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if occupied != set(range(total_bits)):
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raise ValueError("diagram layout has undocumented gaps")
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def dma_fields(root: Path) -> list[dict]:
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source = (root / "crt/include/retrosoc/hal/dma.h").read_text(encoding="utf-8")
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matches = re.findall(r"typedef\s+struct\s*\{([^}]+)\}\s*rs_dma_tcd_t\s*;", source)
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if len(matches) != 1:
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raise ValueError("DMA TCD structure missing or ambiguous")
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members = re.findall(r"(u?int)(16|32)_t\s+(\w+)\s*;", matches[0])
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if re.sub(r"(?:u?int)(?:16|32)_t\s+\w+\s*;", "", matches[0]).strip():
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raise ValueError("unreviewed DMA TCD member type")
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fields, offset = [], 0
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for signed, width, name in members:
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bits = int(width)
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role = "reserved" if name.startswith("reserved") else "writeback" if name in {
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"crc_result", "status", "bytes_done", "error_status"} else "configuration"
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fields.append({"name": name, "lsb": offset * 8, "bits": bits, "offset": offset,
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"role": role, "signed": signed == "int"})
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offset += bits // 8
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validate_fields(fields, 512)
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return fields
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def apu_formats(root: Path) -> dict:
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path = root / "scripts/apu_isa.py"
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source = path.read_text(encoding="utf-8")
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declarations = re.findall(r"\(self\.(\w+),\s*(\d+),\s*(\d+)\)", source)
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aliases = {"instruction_class": "class", "opcode": "opcode", "predicate": "predicate",
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"dst": "dst", "src0": "src0", "src1": "src1", "aux": "aux", "immediate": "immediate"}
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if len(declarations) != 8 or {row[0] for row in declarations} != aliases.keys():
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raise ValueError("APU encoder field inventory changed")
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rtl = (root / "rtl/ip/multimedia/apu_microcode_pkg.sv").read_text(encoding="utf-8")
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fields = []
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for name, width, shift in declarations:
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bits, lsb = int(width), int(shift)
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slices = set(re.findall(r"s_" + aliases[name] + r"\s*=\s*instruction_i\[(\d+):(\d+)\]", rtl))
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if slices != {(str(lsb + bits - 1), str(lsb))}:
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raise ValueError("APU encoder/RTL diagram slice mismatch")
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fields.append({"name": name, "label": aliases[name].upper(), "bits": bits, "lsb": lsb})
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validate_fields(fields, 64)
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spec = importlib.util.spec_from_file_location("publication_apu_diagram_isa", path)
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if spec is None or spec.loader is None:
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raise ValueError("APU encoder could not be loaded")
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isa = importlib.util.module_from_spec(spec)
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sys.modules[spec.name] = isa
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spec.loader.exec_module(isa)
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defines = (root / "rtl/ip/multimedia/apu_define.svh").read_text(encoding="utf-8")
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for suffix, value in (("CLASS_CONTROL", int(isa.InstructionClass.CONTROL)),
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("CLASS_SCALAR", int(isa.InstructionClass.SCALAR)),
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("CONTROL_WAIT", int(isa.ControlOpcode.WAIT)),
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("SCALAR_MOVI", int(isa.ScalarOpcode.MOVI)),
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("PRED_ALWAYS", 0)):
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found = re.findall(r"^`define\s+APB4_APU__MC_" + suffix + r"\s+(\S+)", defines, re.M)
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if len(found) != 1 or number(found[0]) != value:
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raise ValueError("APU example opcode/predicate differs from RTL")
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limits = {}
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legacy = re.findall(r"^`define\s+APB4_APU__APUMC_MAX_INSTRUCTIONS\s+(\d+)", defines, re.M)
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if legacy != [str(isa.APUMC_MAX_INSTRUCTIONS)]:
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raise ValueError("APU legacy image capacity differs from the encoder")
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for version in ("V1", "V2"):
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maximum = re.findall(r"^`define\s+APB4_APU__APUMC_MAX_INSTRUCTIONS_" + version + r"\s+(\d+)", defines, re.M)
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if maximum != [str(getattr(isa, "APUMC_MAX_INSTRUCTIONS_" + version))]:
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raise ValueError("APU control-store capacity differs from the encoder")
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limits[version.lower()] = int(maximum[0])
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instructions = (
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("SCALAR.MOVI: r1 = 0x12345678", isa.Instruction(int(isa.InstructionClass.SCALAR), int(isa.ScalarOpcode.MOVI), dst=1, immediate=0x12345678)),
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("CONTROL.WAIT: DMA source", isa.Instruction(int(isa.InstructionClass.CONTROL), int(isa.ControlOpcode.WAIT), aux=isa.WAIT_SOURCES.index("dma"))),
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)
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examples = []
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for title, instruction in instructions:
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word = instruction.encode()
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if isa.Instruction.decode(word) != instruction:
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raise ValueError("APU instruction diagram failed round-trip encoding")
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examples.append({"title": title, "word": f"0x{word:016X}",
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"values": {name: getattr(instruction, name) for name in aliases}})
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return {"bits": 64, "fields": fields, "examples": examples, "max_instructions": limits["v2"], "image_limits": limits,
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"families": instruction_families(isa, defines)}
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def uart_fifo(root: Path) -> dict:
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source = (root / "rtl/ip/serial/uart_reg.sv").read_text(encoding="utf-8")
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result = {}
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for direction in ("Tx", "Rx"):
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depth = re.findall(r"parameter\s+int\s+" + direction + r"FifoDepth\s*=\s*(\d+)", source)
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fifo = re.findall(r"fifo\s*#\s*\((.*?)\)\s+u_" + direction.lower() + r"_fifo\s*\(", source, re.S)
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if len(depth) != 1 or len(fifo) != 1:
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raise ValueError("UART FIFO instance missing or ambiguous")
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# Select the final declaration before the named instance, not a preceding FIFO.
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widths = re.findall(r"\.DATA_WIDTH\s*\((\d+)\)", fifo[0])
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result[direction.lower()] = {"depth": int(depth[0]), "bits": int(widths[-1])}
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if result != {"tx": {"depth": 64, "bits": 8}, "rx": {"depth": 64, "bits": 12}}:
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raise ValueError("review UART storage diagram after FIFO geometry change")
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return result
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def validate_circuit(root: Path, circuit: dict) -> None:
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nodes, ports = {}, {}
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for node in circuit["nodes"]:
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if node["id"] in nodes:
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raise ValueError("duplicate circuit node")
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nodes[node["id"]] = node
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if not node.get("sources") or not node.get("title"):
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raise ValueError("circuit node lacks source/title")
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instance = node.get("instance_source", {})
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if any(instance[key] not in node["sources"] for key in ("file", "declaration_file") if key in instance):
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raise ValueError("circuit instance declaration is outside its source inventory")
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for port in node["ports"]:
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key = node["id"] + "." + port["id"]
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if key in ports or port["side"] not in {"north", "south", "east", "west"}:
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raise ValueError("duplicate or invalid circuit port")
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width_valid = (type(port["width"]) is int and port["width"] > 0) or (
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port["width"] is None and port.get("bundle") is True)
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if port["direction"] not in {"in", "out"} or not width_valid:
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raise ValueError("invalid circuit port direction/width")
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ports[key] = port
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seen = set()
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for edge in circuit["edges"]:
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src, dst = edge["from"], edge["to"]
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if src not in ports or dst not in ports or (src, dst) in seen:
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raise ValueError("missing or duplicate circuit connection")
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if ports[src]["direction"] != "out" or ports[dst]["direction"] != "in":
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raise ValueError("circuit connection direction mismatch")
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if ports[src]["width"] != ports[dst]["width"] or edge["kind"] not in {"control", "data"}:
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raise ValueError("circuit connection width/kind mismatch")
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displayed_width = re.search(r"/\s*(\d+)$", edge.get("label", ""))
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if displayed_width and ports[src]["width"] is not None and int(displayed_width[1]) != ports[src]["width"]:
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raise ValueError("circuit label width differs from the bound port width")
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if not edge.get("bindings") or not edge.get("label"):
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raise ValueError("circuit connection lacks source binding")
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validate_bindings(root, edge["bindings"])
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seen.add((src, dst))
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validate_instance_connections(root, circuit)
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def collect_diagrams(root: Path, spec: dict, regions: list[dict], system: dict) -> dict:
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for relative in dependencies(spec):
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path = root / relative
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if Path(relative).is_absolute() or ".." in Path(relative).parts or not path.resolve().is_relative_to(root.resolve()) or not path.is_file():
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raise ValueError("missing or invalid diagram source")
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validate_bindings(root, spec["bindings"])
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additional = json.loads((root / spec["circuit_catalog"]).read_text(encoding="utf-8"))
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if set(additional) & set(spec["circuits"]):
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raise ValueError("duplicate circuit illustration identifier")
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circuits = {**spec["circuits"], **additional}
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index = json.loads((root / "publications/datasheets/chapter-index.json").read_text(encoding="utf-8"))
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expected = {row["id"] for row in index} | {"system-fabric", "system-clocks", "system-media", "system-mpw"}
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if set(circuits) != expected:
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raise ValueError("full-document circuit coverage changed")
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for circuit in circuits.values():
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validate_circuit(root, circuit)
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validate_fields(spec["sdio_command"], 48)
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command_fields = [(f["name"], f["lsb"], f["bits"]) for f in spec["sdio_command"]]
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if command_fields != [("start", 47, 1), ("direction", 46, 1), ("command", 40, 6),
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("argument", 8, 32), ("crc7", 1, 7), ("end", 0, 1)]:
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raise ValueError("SDIO field order differs from the bound transmitter assembly")
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dts = (root / "app/ports/linux/linux/retrosoc_hp.dts").read_text(encoding="utf-8")
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if "riscv,cbom-block-size" in dts:
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raise ValueError("review cache-maintenance diagram after platform granule change")
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smoke = (root / "app/ports/linux/smoke/start.S").read_text(encoding="utf-8")
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if (".insn r 0x0b, 0x0, 0x01, x0, a0, x5" not in smoke
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or ".insn r 0x0b, 0x0, 0x01, x0, a0, x6" not in smoke
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or "csrs 0x7c0, t0" not in smoke):
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raise ValueError("review cache-maintenance diagram after platform maintenance-operation change")
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windows = [{k: r[k] for k in ("symbol", "base", "size", "base_hex", "end_hex", "size_label")}
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for r in regions if r["size"] > 4096 and r["route"] in {"axi4", "ram"} and r["kind"] == "active"]
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if not windows or any(r["base"] + r["size"] > 1 << 32 for r in windows):
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raise ValueError("memory diagram has an invalid address window")
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if any(int(r["base_hex"], 16) != r["base"] or int(r["end_hex"], 16) != r["base"] + r["size"] - 1 for r in windows):
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raise ValueError("memory diagram range labels disagree with numeric bounds")
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layouts = collect_layouts(root, spec["layout_catalog"], system)
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for layout in layouts.values():
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validate_bindings(root, layout.get("bindings", []))
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for row in layout.get("rows", [layout]):
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validate_fields(row["fields"], row["bits"])
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groups = row.get("display_groups", layout.get("display_groups"))
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if groups is not None:
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indexes = [index for lo, hi in groups for index in range(lo, hi + 1)]
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if indexes != list(range(len(row["fields"]))):
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raise ValueError("compressed binary diagram drops or repeats fields")
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storage = collect_storage(root, spec["storage_catalog"], regions, system, layouts)
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for record in storage.values():
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validate_bindings(root, record.get("bindings", []))
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return {"sources": sorted(dependencies(spec)), "dma_tcd": dma_fields(root),
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"sdio_command": copy.deepcopy(spec["sdio_command"]), "apu": apu_formats(root),
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"uart_fifo": uart_fifo(root), "windows": sorted(windows, key=lambda r: r["base"]),
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"cache": {"granule": 64, "offset": 16, "length": 64, "end": 80, "covered_bytes": 128},
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"circuits": circuits, "layouts": layouts, "storage": storage,
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"soc_architecture": collect_soc_diagram(root, spec["soc_architecture_catalog"], regions) if spec.get("soc_architecture_catalog") else {}}
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