mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-04 22:32:36 +00:00
maksyuki
83fe263e40
Add isolated default and camera LibreLane IO profiles, assigning camera inputs to the pixel clock and keeping ordinary GPIO constraints in default. Separate generated output roots and synchronize the commercial clock-domain inventory with the P9 DVP domain. Retained validation: nine LibreLane scenario tests and 50 commercial-flow/ Tiny reset-inventory tests pass. Constraints retain development assumptions; no commercial EDA, physical signoff or board timing qualification is claimed. Specification: docs/ip/tiny-soc.md, TINY-R2-P9.
234 lines
10 KiB
Python
234 lines
10 KiB
Python
"""Tests for the Tiny IHP130 LibreLane chip flow."""
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from __future__ import annotations
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import importlib.util
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import re
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import subprocess
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from pathlib import Path
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from types import SimpleNamespace
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import pytest
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ROOT = Path(__file__).resolve().parents[1]
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PIN_MAP = ROOT / "rtl/tiny/pin_map/pin_map.json"
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DOMAINS = ROOT / "rtl/tiny/integration/clock_reset_domains.json"
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FLOW_ROOT = ROOT / "physical/librelane/tiny"
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BONDPAD_LEF = ROOT / "physical/librelane/bondpad/bondpad_70x70.lef"
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def load_module(name: str, path: Path):
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spec = importlib.util.spec_from_file_location(name, path)
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assert spec is not None and spec.loader is not None
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module = importlib.util.module_from_spec(spec)
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spec.loader.exec_module(module)
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return module
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def chip_arguments(tmp_path: Path) -> SimpleNamespace:
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return SimpleNamespace(
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pin_map=PIN_MAP,
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rtl=tmp_path / "retrosoc_tiny_asic_sources.sv",
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sdc=tmp_path / "retrosoc_tiny_chip.sdc",
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pdn=FLOW_ROOT / "pdn_cfg.tcl",
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bondpad_gds=tmp_path / "bondpad_70x70.gds",
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bondpad_lef=BONDPAD_LEF,
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sram_vh=FLOW_ROOT / "sram_blackboxes.vh",
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ext_clk_hz=24_000_000,
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have_sram_macro=True,
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sram_size_kib=128,
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output=tmp_path / "config.json",
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)
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def test_chip_config_places_every_signal_and_power_pad_once(tmp_path: Path) -> None:
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module = load_module(
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"retrosoc_tiny_librelane_config", FLOW_ROOT / "scripts/generate_chip_config.py"
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)
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config = module.build_config(chip_arguments(tmp_path))
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sides = {name: config[f"PAD_{name.upper()}"] for name in module.SIDE_ORDER}
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placed = [instance for side in module.SIDE_ORDER for instance in sides[side]]
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assert len(placed) == 84
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assert len(placed) == len(set(placed))
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assert {side: len(instances) for side, instances in sides.items()} == {
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"south": 19,
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"east": 24,
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"north": 17,
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"west": 24,
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}
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assert sum(item.startswith("vdd_pads[") for item in placed) == 8
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assert sum(item.startswith("vss_pads[") for item in placed) == 8
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assert sum(item.startswith("iovdd_pads[") for item in placed) == 8
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assert sum(item.startswith("iovss_pads[") for item in placed) == 8
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assert "u_extclk_i_pad.u_sg13g2_IOPadIn" in sides["south"]
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assert "u_jtag_tck_i_pad.u_sg13g2_IOPadIn" in sides["south"]
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assert "u_uart0_tx_o_pad.u_sg13g2_IOPadOut4mA" in sides["south"]
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assert "u_xpi_sck_o_pad.u_sg13g2_IOPadOut4mA" in sides["north"]
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assert "u_gpio_0_io_pad.u_sg13g2_IOPadInOut4mA" in sides["east"]
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assert "u_gpio_15_io_pad.u_sg13g2_IOPadInOut4mA" in sides["east"]
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assert "u_gpio_16_io_pad.u_sg13g2_IOPadInOut4mA" in sides["west"]
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assert "u_gpio_31_io_pad.u_sg13g2_IOPadInOut4mA" in sides["west"]
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assert config["meta"] == {"version": 3, "flow": "Chip"}
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assert config["DESIGN_NAME"] == "retrosoc_tiny_asic"
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assert config["DIE_AREA"] == [0, 0, 4700, 4700]
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assert config["CORE_AREA"] == [365, 365, 4335, 4335]
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assert config["CLOCK_PORT"] == ["extclk_i_pad", "jtag_tck_i_pad"]
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assert config["CLOCK_PERIOD"] == 1_000_000_000 / 24_000_000
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assert config["PL_TARGET_DENSITY_PCT"] == 45
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assert config["USE_SLANG"] is True
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assert config["SLANG_ARGUMENTS"] == ["--keep-hierarchy"]
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assert config["SYNTH_HIERARCHY_MODE"] == "deferred_flatten"
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assert config["SYNTH_KEEP_HIERARCHY_MODULES"] == [
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"sg13g2_IOPadVdd",
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"sg13g2_IOPadVss",
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"sg13g2_IOPadIOVdd",
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"sg13g2_IOPadIOVss",
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]
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assert config["RUN_CTS"] is False
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assert config["ERROR_ON_SYNTH_CHECKS"] is False
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assert config["EXTRA_EXCLUDED_CELLS"] == ["sg13g2_IOPad*"]
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assert config["VDD_NETS"] == ["VDD"]
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assert config["GND_NETS"] == ["VSS"]
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assert config["PAD_CFG"].endswith("physical/librelane/tiny/pad_cfg.tcl")
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assert config["PDN_ENABLE_PINS"] is True
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assert config["ERROR_ON_PDN_VIOLATIONS"] is True
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assert config["STA_EXTRA_CORNER_TCL_FILE"].endswith(
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"physical/librelane/tiny/sta_report_limit.tcl"
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)
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assert config["PAD_BONDPAD_NAME"] == "bondpad_70x70"
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assert set(config["MACROS"]) == {"RM_IHPSG13_1P_1024x32_c2_bm_bist"}
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def test_chip_config_covers_every_onchip_sram_bank(tmp_path: Path) -> None:
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module = load_module(
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"retrosoc_tiny_librelane_sram_config", FLOW_ROOT / "scripts/generate_chip_config.py"
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)
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config = module.build_config(chip_arguments(tmp_path))
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macro = config["MACROS"]["RM_IHPSG13_1P_1024x32_c2_bm_bist"]
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assert len(macro["instances"]) == 32
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assert (
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"u_soc.u_sram.gen_group[0].u_group.gen_bank[0].u_ram.u_mem" in macro["instances"]
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)
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assert (
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"u_soc.u_sram.gen_group[3].u_group.gen_bank[7].u_ram.u_mem" in macro["instances"]
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)
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for instance in macro["instances"].values():
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x, y = instance["location"]
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assert 365 <= x <= 4335
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assert 365 <= y <= 4335
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assert instance["orientation"] == "N"
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assert len(config["PDN_MACRO_CONNECTIONS"]) == 64
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assert any(
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"gen_bank.*0.*\\.u_ram" in connection
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for connection in config["PDN_MACRO_CONNECTIONS"]
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)
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blackboxes = (FLOW_ROOT / "sram_blackboxes.vh").read_text(encoding="utf-8")
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assert "module RM_IHPSG13_1P_1024x32_c2_bm_bist" in blackboxes
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assert "RM_IHPSG13_1P_4096x16_c3_bm_bist" not in blackboxes
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def test_chip_sdc_is_pad_aware_and_does_not_false_path_all_io() -> None:
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module = load_module(
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"retrosoc_tiny_librelane_sdc", FLOW_ROOT / "scripts/generate_sdc.py"
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)
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arguments = SimpleNamespace(
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domains=DOMAINS,
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pin_map=PIN_MAP,
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ext_clk_hz=24_000_000,
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)
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sdc = module.render(arguments)
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assert "u_extclk_i_pad.u_sg13g2_IOPadIn/p2c" in sdc
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assert "u_jtag_tck_i_pad.u_sg13g2_IOPadIn/p2c" in sdc
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assert "u_clock_buffer.u_sg13g2_buf_1/X" in sdc
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assert "create_clock -name clk_external -period 41.6666666667" in sdc
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assert "create_clock -name clk_jtag -period 100" in sdc
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assert "create_generated_clock -name clk_system" in sdc
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assert "set_clock_groups -name retrosoc_async -asynchronous" in sdc
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assert "-group [get_clocks {clk_external clk_system}]" in sdc
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assert "-group [get_clocks {clk_jtag}]" in sdc
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assert "set_input_delay -max" in sdc
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assert "set_output_delay -max" in sdc
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assert "set_false_path -from $reset_ext_rst_n_i_pad" in sdc
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assert "set_false_path -from $reset_jtag_trst_n_i_pad" in sdc
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assert "set_false_path -from [all_inputs]" not in sdc
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assert "set_false_path -to [all_outputs]" not in sdc
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assert "clk_pixel" not in sdc
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@pytest.mark.parametrize("profile", ["default", "camera"])
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def test_camera_io_clock_scenario(profile: str, tmp_path: Path) -> None:
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module = load_module("tiny_sdc_scenario", FLOW_ROOT / "scripts/generate_sdc.py")
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sdc = module.render(SimpleNamespace(domains=DOMAINS, pin_map=PIN_MAP,
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ext_clk_hz=24_000_000, io_profile=profile))
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groups = {name: set(ports.split()) for name, ports in re.findall(
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r"set (\w+_(?:inputs|outputs)) \[get_ports \{([^}]*)\}\]", sdc)}
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camera = {f"gpio_{pin}_io_pad" for pin in (*range(12, 20), 21, 22)}
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config_module = load_module("tiny_config_scenario", FLOW_ROOT / "scripts/generate_chip_config.py")
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arguments = chip_arguments(tmp_path)
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arguments.io_profile = profile
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config = config_module.build_config(arguments)
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if profile == "camera":
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assert groups["pixel_inputs"] == camera
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assert not camera & groups["external_inputs"]
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assert not camera & groups["external_outputs"]
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assert "gpio_20_io_pad" not in groups["external_inputs"]
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assert "gpio_20_io_pad" not in groups["external_outputs"]
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assert "set_input_delay -min 0 -clock clk_pixel $pixel_inputs" in sdc
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assert "set_input_delay -max 16.6666666666 -clock clk_pixel $pixel_inputs" in sdc
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assert "-group [get_clocks {clk_pixel}]" in sdc
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assert config["CLOCK_PORT"] == ["extclk_i_pad", "jtag_tck_i_pad", "gpio_20_io_pad"]
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else:
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assert "pixel_inputs" not in groups
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assert camera | {"gpio_20_io_pad"} <= groups["external_inputs"]
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assert camera | {"gpio_20_io_pad"} <= groups["external_outputs"]
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assert "clk_pixel" not in sdc
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assert config["CLOCK_PORT"] == ["extclk_i_pad", "jtag_tck_i_pad"]
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assert "gpio_23_io_pad" in groups["external_outputs"]
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def test_camera_io_profile_rejects_unknown_value(tmp_path: Path) -> None:
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module = load_module("tiny_sdc_bad_scenario", FLOW_ROOT / "scripts/generate_sdc.py")
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with pytest.raises(ValueError, match="IO profile"):
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module.render(SimpleNamespace(io_profile="both"))
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module = load_module("tiny_config_bad_scenario", FLOW_ROOT / "scripts/generate_chip_config.py")
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arguments = chip_arguments(tmp_path)
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arguments.io_profile = "both"
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with pytest.raises(ValueError, match="IO profile"):
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module.build_config(arguments)
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@pytest.mark.parametrize("profile", ["default", "camera"])
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def test_camera_make_scenario_isolated(profile: str) -> None:
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result = subprocess.run([
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"make", "--no-print-directory", "-n", "CONFIG=configs/ci/ihp130-tiny.mk",
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"SOC=TINY", "PDK=IHP130", f"LIBRELANE_IO_PROFILE={profile}", "librelane-input",
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], cwd=ROOT, capture_output=True, text=True, check=False)
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assert result.returncode == 0, result.stdout + result.stderr
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directory = "chip-camera" if profile == "camera" else "chip"
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assert f"physical/librelane/tiny/{directory}/input/retrosoc_tiny_chip.sdc" in result.stdout
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assert result.stdout.count(f"--io-profile {profile}") == 2
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def test_tiny_flow_exposes_chip_target_only() -> None:
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makefile = (FLOW_ROOT / "Makefile").read_text(encoding="utf-8")
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top_makefile = (ROOT / "Makefile").read_text(encoding="utf-8")
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assert "librelane-chip:" in makefile
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assert "librelane-core:" not in makefile
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assert "--soc TINY" in makefile
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assert "--source-filelist-dir" in makefile
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assert re.search(r"ifeq \(\$\(SOC\),TINY\)\ninclude physical/librelane/tiny/Makefile", top_makefile)
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assert "include physical/librelane/mini/Makefile" in top_makefile
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doctor = (FLOW_ROOT / "scripts/doctor.py").read_text(encoding="utf-8")
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assert "EXPECTED_SIGNAL_PADS = 52" in doctor
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pad_cfg = (FLOW_ROOT / "pad_cfg.tcl").read_text(encoding="utf-8")
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assert "vdd sg13g2_IOPadVdd 8" in pad_cfg
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assert "iovss sg13g2_IOPadIOVss 8" in pad_cfg
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pdn = (FLOW_ROOT / "pdn_cfg.tcl").read_text(encoding="utf-8")
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assert "RM_IHPSG13_1P_1024x32_c2_bm_bist" in pdn
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assert "RM_IHPSG13_1P_4096x16_c3_bm_bist" not in pdn
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