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https://github.com/retroSoC/retroSoC.git
synced 2026-11-06 14:55:14 +00:00
maksyuki
f5b373fd65
- Added timestamp normalization to function in , allowing for optional timestamp input. - Updated command-line interface to accept a timestamp argument for generating deterministic build variant IDs. - Modified in to include a build timestamp in the environment variables. - Introduced a new test suite in to validate the pin-map generator, including tests for duplicate pads and invalid entries. - Added a test for ensuring the regression runner uses a consistent build timestamp. - Created a new SystemVerilog testbench for the APB4 interface bridge to verify correct signal crossing.
45 lines
1.3 KiB
Systemverilog
45 lines
1.3 KiB
Systemverilog
`timescale 1ns / 1ps
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module apb4_if_bridge_tb;
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logic pclk = 1'b0;
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logic presetn = 1'b0;
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apb4_pure_if apb_pure ();
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apb4_if apb_timed (
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.pclk (pclk),
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.presetn(presetn)
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);
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apb4_if_bridge u_apb4_if_bridge (
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.apb_pure(apb_pure),
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.timed (apb_timed)
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);
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initial begin
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apb_pure.paddr = 32'h1234_5678;
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apb_pure.pprot = 3'b101;
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apb_pure.psel = 1'b1;
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apb_pure.penable = 1'b1;
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apb_pure.pwrite = 1'b1;
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apb_pure.pwdata = 32'hCAFE_BABE;
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apb_pure.pstrb = 4'b1101;
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apb_timed.pready = 1'b1;
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apb_timed.prdata = 32'hDEAD_BEEF;
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apb_timed.pslverr = 1'b0;
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#1;
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if ({apb_timed.paddr, apb_timed.pprot, apb_timed.psel, apb_timed.penable,
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apb_timed.pwrite, apb_timed.pwdata, apb_timed.pstrb} !==
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{apb_pure.paddr, apb_pure.pprot, apb_pure.psel, apb_pure.penable,
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apb_pure.pwrite, apb_pure.pwdata, apb_pure.pstrb}) begin
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$fatal(1, "APB request fields did not cross the bridge");
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end
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if ({apb_pure.pready, apb_pure.prdata, apb_pure.pslverr} !==
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{apb_timed.pready, apb_timed.prdata, apb_timed.pslverr}) begin
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$fatal(1, "APB response fields did not cross the bridge");
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end
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$display("apb4 interface bridge test passed");
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$finish;
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end
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endmodule
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