mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-06 06:55:14 +00:00
maksyuki
5c65fcca27
- Updated axi4_async_bridge_tb.sv to include unilateral reset handling in the test. - Enhanced axi4_target_guard_tb.sv with a new task for read beat normalization and additional read tests. - Introduced hp_axi4_mux3_rr_tb.sv to test round-robin arbitration for multiple AXI4 interfaces. - Expanded test_apu.py to include tests for APU stream router, DMA, ring scheduler, and integrated DMA/ring/backend functionality. - Added new test cases for APU-P2 Gateway A round-robin fairness. - Updated test_clock_reset_domains.py to include APU data crossing. - Enhanced test_script_tools.py to scope formal filelists for APU and Gateway A.
344 lines
12 KiB
Systemverilog
344 lines
12 KiB
Systemverilog
`timescale 1ns / 1ps
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`include "apu_define.svh"
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`include "soc_irq_config.svh"
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module apu_irq_topology_tb;
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localparam logic [31:0] ApuBase = 32'h1001_3000;
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localparam logic [11:0] Resource7Owner = 12'h1e0;
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localparam logic [11:0] Resource7Control = 12'h1e4;
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localparam logic [11:0] Resource7Fault = 12'h1ec;
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logic clk_i = 1'b0;
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logic rst_n_i = 1'b0;
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logic s_apu_idle;
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logic s_apu_irq_raw;
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logic [ 7:0] s_resource_idle;
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logic [ 7:0] s_resource_block_ack;
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logic [ 7:0] s_resource_irq_raw;
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logic [ 7:0][1:0] s_resource_owner;
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logic [ 7:0] s_resource_owner_lock;
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logic [ 7:0] s_resource_quiesce;
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logic [ 7:0] s_resource_reset;
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logic [ 7:0] s_resource_irq_lp;
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logic [ 7:0] s_resource_irq_hp;
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logic [ 6:0] s_resource_irq_lp_compact;
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logic [ 6:0] s_resource_irq_hp_compact;
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logic s_resource_fault_irq;
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logic s_cache_clean;
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logic [`SOC_IRQ_APB4_PERIPH_WIDTH-1:0] s_apb4_periph_irq;
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logic [`SOC_IRQ_APB4_SYSTEM_WIDTH-1:0] s_apb4_system_irq;
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logic [ `SOC_IRQ_VECTOR_WIDTH-1:0] s_irq;
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logic [ 31:0] s_hp_plic_source;
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logic [ 1:0] s_hp_plic_context_irq;
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logic [ 31:0] s_value;
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apb4_if u_apu_apb4_if (
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.pclk (clk_i),
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.presetn(rst_n_i)
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);
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apb4_if u_resource_apb4_if (
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.pclk (clk_i),
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.presetn(rst_n_i)
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);
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apb4_if u_plic_apb4_if (
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.pclk (clk_i),
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.presetn(rst_n_i)
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);
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axi4_if #(
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.ADDR_WIDTH(32),
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.DATA_WIDTH(32),
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.ID_WIDTH (1),
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.USER_WIDTH(1)
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) u_apu_axi4_if (
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clk_i,
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rst_n_i
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);
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axi4_stream_if #(
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.DATA_WIDTH(32)
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) u_dma_tx_axis (
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clk_i,
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rst_n_i
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);
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axi4_stream_if #(
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.DATA_WIDTH(32)
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) u_dma_rx_axis (
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clk_i,
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rst_n_i
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);
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axi4_stream_if #(
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.DATA_WIDTH(32)
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) u_i2s_tx_axis (
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clk_i,
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rst_n_i
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);
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axi4_stream_if #(
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.DATA_WIDTH(32)
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) u_i2s_rx_axis (
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clk_i,
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rst_n_i
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);
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always #5 clk_i = ~clk_i;
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assign s_resource_idle = {s_apu_idle, 7'h7f};
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assign s_resource_block_ack = {
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s_apu_idle && (s_resource_quiesce[7] || s_resource_reset[7]), 7'd0
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};
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assign s_resource_irq_raw = {s_apu_irq_raw, 7'd0};
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assign s_resource_irq_lp_compact = {s_resource_irq_lp[7:6], s_resource_irq_lp[4:0]};
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assign s_resource_irq_hp_compact = {s_resource_irq_hp[7:6], s_resource_irq_hp[4:0]};
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assign s_apb4_periph_irq = {s_resource_irq_lp_compact[6], 23'd0};
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assign s_apb4_system_irq = '0;
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assign s_hp_plic_source = {21'd0, s_resource_irq_hp_compact[6], 10'd0};
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`include "soc_irq_wiring.svh"
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apb4_apu u_apu (
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.clk_i (clk_i),
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.rst_n_i (rst_n_i),
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.owner_i (s_resource_owner[7]),
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.owner_lock_i (s_resource_owner_lock[7]),
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.quiesce_i (s_resource_quiesce[7]),
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.resource_reset_i (s_resource_reset[7]),
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.bridge_epoch_i (8'd0),
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.i2s_tx_underrun_i(1'b0),
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.i2s_rx_overrun_i (1'b0),
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.apb4 (u_apu_apb4_if),
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.axi4 (u_apu_axi4_if),
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.dma_tx_axis (u_dma_tx_axis),
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.dma_rx_axis (u_dma_rx_axis),
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.i2s_tx_axis (u_i2s_tx_axis),
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.i2s_rx_axis (u_i2s_rx_axis),
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.idle_o (s_apu_idle),
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.irq_o (s_apu_irq_raw)
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);
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resource_controller #(
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.ResourceCount(8)
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) u_resource_controller (
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.clk_i (clk_i),
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.rst_n_i (rst_n_i),
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.idle_i (s_resource_idle),
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.block_ack_i (s_resource_block_ack),
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.irq_i (s_resource_irq_raw),
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.cache_request_i(1'b0),
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.cache_clean_o (s_cache_clean),
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.owner_o (s_resource_owner),
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.owner_lock_o (s_resource_owner_lock),
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.quiesce_o (s_resource_quiesce),
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.reset_o (s_resource_reset),
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.irq_lp_o (s_resource_irq_lp),
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.irq_hp_o (s_resource_irq_hp),
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.fault_irq_o (s_resource_fault_irq),
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.apb4 (u_resource_apb4_if)
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);
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apb4_plic u_hp_plic (
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.clk_i (clk_i),
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.rst_n_i (rst_n_i),
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.source_i (s_hp_plic_source),
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.apb4 (u_plic_apb4_if),
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.context_irq_o(s_hp_plic_context_irq)
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);
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task automatic drive_apb_idle;
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begin
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u_apu_apb4_if.paddr = 32'd0;
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u_apu_apb4_if.pprot = 3'd0;
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u_apu_apb4_if.psel = 1'b0;
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u_apu_apb4_if.penable = 1'b0;
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u_apu_apb4_if.pwrite = 1'b0;
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u_apu_apb4_if.pwdata = 32'd0;
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u_apu_apb4_if.pstrb = 4'd0;
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u_resource_apb4_if.paddr = 32'd0;
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u_resource_apb4_if.pprot = 3'd0;
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u_resource_apb4_if.psel = 1'b0;
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u_resource_apb4_if.penable = 1'b0;
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u_resource_apb4_if.pwrite = 1'b0;
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u_resource_apb4_if.pwdata = 32'd0;
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u_resource_apb4_if.pstrb = 4'd0;
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u_plic_apb4_if.paddr = 32'd0;
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u_plic_apb4_if.pprot = 3'd0;
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u_plic_apb4_if.psel = 1'b0;
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u_plic_apb4_if.penable = 1'b0;
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u_plic_apb4_if.pwrite = 1'b0;
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u_plic_apb4_if.pwdata = 32'd0;
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u_plic_apb4_if.pstrb = 4'd0;
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end
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endtask
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task automatic apu_write(input logic [11:0] offset_i, input logic [31:0] data_i);
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begin
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@(negedge clk_i);
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u_apu_apb4_if.paddr = ApuBase + offset_i;
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u_apu_apb4_if.pwdata = data_i;
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u_apu_apb4_if.pstrb = 4'hf;
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u_apu_apb4_if.pwrite = 1'b1;
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u_apu_apb4_if.psel = 1'b1;
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u_apu_apb4_if.penable = 1'b0;
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@(negedge clk_i);
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u_apu_apb4_if.penable = 1'b1;
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while (!u_apu_apb4_if.pready) @(negedge clk_i);
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if (u_apu_apb4_if.pslverr) $fatal(1, "APU topology write failed at %h", offset_i);
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@(negedge clk_i);
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u_apu_apb4_if.psel = 1'b0;
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u_apu_apb4_if.penable = 1'b0;
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u_apu_apb4_if.pwrite = 1'b0;
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u_apu_apb4_if.pstrb = 4'd0;
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end
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endtask
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task automatic resource_write(input logic [11:0] offset_i, input logic [31:0] data_i,
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input logic expected_err_i);
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begin
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@(negedge clk_i);
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u_resource_apb4_if.paddr = {20'd0, offset_i};
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u_resource_apb4_if.pwdata = data_i;
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u_resource_apb4_if.pstrb = 4'hf;
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u_resource_apb4_if.pwrite = 1'b1;
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u_resource_apb4_if.psel = 1'b1;
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u_resource_apb4_if.penable = 1'b0;
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@(negedge clk_i);
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u_resource_apb4_if.penable = 1'b1;
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while (!u_resource_apb4_if.pready) @(negedge clk_i);
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if (u_resource_apb4_if.pslverr != expected_err_i) begin
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$fatal(1, "Resource topology write response mismatch at %h", offset_i);
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end
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@(negedge clk_i);
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u_resource_apb4_if.psel = 1'b0;
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u_resource_apb4_if.penable = 1'b0;
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u_resource_apb4_if.pwrite = 1'b0;
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u_resource_apb4_if.pstrb = 4'd0;
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end
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endtask
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task automatic plic_write(input logic [25:0] offset_i, input logic [31:0] data_i);
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begin
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@(negedge clk_i);
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u_plic_apb4_if.paddr = {6'd0, offset_i};
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u_plic_apb4_if.pwdata = data_i;
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u_plic_apb4_if.pstrb = 4'hf;
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u_plic_apb4_if.pwrite = 1'b1;
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u_plic_apb4_if.psel = 1'b1;
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u_plic_apb4_if.penable = 1'b0;
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@(negedge clk_i);
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u_plic_apb4_if.penable = 1'b1;
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while (!u_plic_apb4_if.pready) @(negedge clk_i);
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if (u_plic_apb4_if.pslverr) $fatal(1, "PLIC topology write failed at %h", offset_i);
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@(negedge clk_i);
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u_plic_apb4_if.psel = 1'b0;
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u_plic_apb4_if.penable = 1'b0;
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u_plic_apb4_if.pwrite = 1'b0;
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u_plic_apb4_if.pstrb = 4'd0;
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end
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endtask
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task automatic plic_read(input logic [25:0] offset_i, output logic [31:0] data_o);
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begin
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@(negedge clk_i);
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u_plic_apb4_if.paddr = {6'd0, offset_i};
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u_plic_apb4_if.pstrb = 4'd0;
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u_plic_apb4_if.pwrite = 1'b0;
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u_plic_apb4_if.psel = 1'b1;
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u_plic_apb4_if.penable = 1'b0;
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@(negedge clk_i);
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u_plic_apb4_if.penable = 1'b1;
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while (!u_plic_apb4_if.pready) @(negedge clk_i);
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if (u_plic_apb4_if.pslverr) $fatal(1, "PLIC topology read failed at %h", offset_i);
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data_o = u_plic_apb4_if.prdata;
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@(negedge clk_i);
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u_plic_apb4_if.psel = 1'b0;
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u_plic_apb4_if.penable = 1'b0;
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end
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endtask
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initial begin
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drive_apb_idle();
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u_apu_axi4_if.awready = 1'b0;
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u_apu_axi4_if.wready = 1'b0;
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u_apu_axi4_if.bid = '0;
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u_apu_axi4_if.bresp = '0;
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u_apu_axi4_if.buser = '0;
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u_apu_axi4_if.bvalid = 1'b0;
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u_apu_axi4_if.arready = 1'b0;
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u_apu_axi4_if.rid = '0;
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u_apu_axi4_if.rdata = '0;
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u_apu_axi4_if.rresp = '0;
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u_apu_axi4_if.rlast = 1'b0;
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u_apu_axi4_if.ruser = '0;
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u_apu_axi4_if.rvalid = 1'b0;
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u_dma_tx_axis.tdata = '0;
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u_dma_tx_axis.tkeep = '1;
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u_dma_tx_axis.tstrb = '1;
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u_dma_tx_axis.tlast = 1'b0;
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u_dma_tx_axis.tid = '0;
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u_dma_tx_axis.tdest = '0;
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u_dma_tx_axis.tuser = '0;
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u_dma_tx_axis.tvalid = 1'b0;
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u_dma_rx_axis.tready = 1'b1;
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u_i2s_tx_axis.tready = 1'b1;
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u_i2s_rx_axis.tdata = '0;
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u_i2s_rx_axis.tkeep = '1;
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u_i2s_rx_axis.tstrb = '1;
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u_i2s_rx_axis.tlast = 1'b0;
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u_i2s_rx_axis.tid = '0;
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u_i2s_rx_axis.tdest = '0;
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u_i2s_rx_axis.tuser = '0;
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u_i2s_rx_axis.tvalid = 1'b0;
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repeat (4) @(posedge clk_i);
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rst_n_i = 1'b1;
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plic_write(26'h000028, 32'd3);
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plic_write(26'h002000, 32'h0000_0400);
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plic_write(26'h200000, 32'd0);
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apu_write(`APB4_APU__IRQ_ENABLE, 32'h0000_0001);
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apu_write(`APB4_APU__IRQ_TEST, 32'h0000_0001);
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repeat (2) @(posedge clk_i);
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#1;
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if ((s_resource_owner[7] != 2'd0) || !s_resource_irq_lp[7] || s_resource_irq_hp[7] ||
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!s_apb4_periph_irq[23] || !s_irq[31] || s_hp_plic_source[10] ||
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s_hp_plic_context_irq[0]) begin
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$fatal(1, "APU event was not delivered exclusively to LP IRQ31");
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end
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resource_write(Resource7Control, 32'h0000_0001, 1'b0);
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resource_write(Resource7Owner, 32'h0000_0101, 1'b0);
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repeat (2) @(posedge clk_i);
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#1;
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if ((s_resource_owner[7] != 2'd1) || !s_resource_owner_lock[7] ||
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s_resource_irq_lp[7] || !s_resource_irq_hp[7] || s_apb4_periph_irq[23] ||
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s_irq[31] || !s_hp_plic_source[10] || !s_hp_plic_context_irq[0]) begin
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$fatal(1, "APU event was not delivered exclusively to HP PLIC source 10");
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end
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plic_read(26'h200004, s_value);
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if (s_value != 32'd10) $fatal(1, "HP PLIC did not claim APU source 10");
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resource_write(Resource7Owner, 32'd0, 1'b1);
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if ((s_resource_owner[7] != 2'd1) || !s_resource_owner_lock[7] || !s_resource_fault_irq) begin
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$fatal(1, "APU owner lock did not preserve HP ownership");
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end
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resource_write(Resource7Fault, 32'h0000_0001, 1'b0);
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if (s_resource_fault_irq) $fatal(1, "APU resource fault did not clear");
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resource_write(Resource7Control, 32'h0000_0003, 1'b0);
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repeat (2) @(posedge clk_i);
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#1;
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if (s_resource_irq_lp[7] || s_resource_irq_hp[7] || s_apb4_periph_irq[23] || s_irq[31] ||
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s_hp_plic_source[10]) begin
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$fatal(1, "APU resource reset did not mask both interrupt routes");
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end
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if (s_resource_fault_irq || s_cache_clean) begin
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$fatal(1, "APU topology test left an unrelated controller output asserted");
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end
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$display("APU-P1 integrated IRQ ownership topology passed");
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$finish;
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end
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initial begin
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repeat (1000) @(posedge clk_i);
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$fatal(1, "APU-P1 IRQ ownership topology timed out");
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end
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endmodule
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