mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-06 14:55:14 +00:00
- Modified DMA error testbench to include crypto input and output AXI4 stream interfaces. - Updated DMA register testbench to integrate crypto AXI4 stream interfaces. - Enhanced SOC IRQ topology test to account for new crypto IRQs. - Added WS2812 DMA testbench modifications for crypto interfaces. - Introduced new Python tests for crypto primitives (AES, SHA, RSA) and APB register paths. - Implemented register parity tests to ensure synchronization between RTL and SDK constants. - Expanded DMA tests to validate crypto streaming endpoints. - Updated memory map tests to include crypto address definitions. - Adjusted SOC topology tests to reflect changes in IRQ mappings and peripheral counts.
164 lines
4.4 KiB
Systemverilog
164 lines
4.4 KiB
Systemverilog
`timescale 1ns / 1ps
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module crypto_rsa_tb;
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localparam int Bits = 64;
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logic clk_i = 1'b0;
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logic rst_n_i = 1'b0;
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logic zeroize_i = 1'b0;
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logic abort_i = 1'b0;
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logic prepare_i = 1'b0;
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logic start_i = 1'b0;
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logic private_i = 1'b0;
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logic [ 11:0] exponent_bits_i = '0;
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logic [Bits-1:0] modulus_i = '0;
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logic [Bits-1:0] exponent_i = '0;
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logic [Bits-1:0] base_i = '0;
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logic busy_o;
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logic done_o;
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logic error_o;
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logic prepared_o;
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logic result_valid_o;
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logic [Bits-1:0] result_o;
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logic [ 31:0] cycles_o;
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logic [ 31:0] progress_o;
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logic mont_start = 1'b0;
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logic [Bits-1:0] mont_left = '0;
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logic [Bits-1:0] mont_right = '0;
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logic mont_busy;
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logic mont_done;
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logic [Bits-1:0] mont_result;
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always #5 clk_i = ~clk_i;
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crypto_rsa_core #(
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.Bits(Bits)
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) u_crypto_rsa_core (
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.clk_i (clk_i),
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.rst_n_i (rst_n_i),
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.zeroize_i (zeroize_i),
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.abort_i (abort_i),
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.prepare_i (prepare_i),
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.start_i (start_i),
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.private_i (private_i),
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.exponent_bits_i(exponent_bits_i),
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.modulus_i (modulus_i),
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.exponent_i (exponent_i),
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.base_i (base_i),
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.busy_o (busy_o),
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.done_o (done_o),
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.error_o (error_o),
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.prepared_o (prepared_o),
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.result_valid_o (result_valid_o),
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.result_o (result_o),
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.cycles_o (cycles_o),
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.progress_o (progress_o)
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);
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crypto_montgomery #(
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.Bits(Bits)
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) u_direct_montgomery (
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.clk_i (clk_i),
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.rst_n_i (rst_n_i),
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.zeroize_i (zeroize_i),
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.start_i (mont_start),
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.left_i (mont_left),
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.right_i (mont_right),
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.modulus_i (modulus_i),
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.n0_prime_i(32'h03030303),
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.busy_o (mont_busy),
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.done_o (mont_done),
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.result_o (mont_result)
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);
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task automatic pulse_prepare;
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begin
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@(negedge clk_i);
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prepare_i = 1'b1;
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@(negedge clk_i);
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prepare_i = 1'b0;
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wait (done_o);
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if (!prepared_o || error_o) begin
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$fatal(1, "RSA modulus preparation failed");
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end
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end
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endtask
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task automatic pulse_start(input logic is_private);
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begin
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@(negedge clk_i);
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private_i = is_private;
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start_i = 1'b1;
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@(negedge clk_i);
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start_i = 1'b0;
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wait (done_o);
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if (!result_valid_o || error_o) begin
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$fatal(1, "RSA modular exponentiation failed");
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end
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end
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endtask
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initial begin
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repeat (3) @(posedge clk_i);
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rst_n_i = 1'b1;
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modulus_i = 64'hffffffea00000055;
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pulse_prepare();
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if (u_crypto_rsa_core.s_r2_q != 64'h00001afbffff7b85) begin
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$fatal(1, "RSA R2 mismatch: %h", u_crypto_rsa_core.s_r2_q);
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end
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if (u_crypto_rsa_core.s_n0_prime_q != 32'h03030303) begin
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$fatal(1, "RSA n0 prime mismatch: %h", u_crypto_rsa_core.s_n0_prime_q);
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end
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@(negedge clk_i);
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mont_left = 64'h0123456789abcdef;
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mont_right = 64'h00001afbffff7b85;
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mont_start = 1'b1;
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@(negedge clk_i);
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mont_start = 1'b0;
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wait (mont_done);
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if (mont_result != 64'h9abcdefafa4fa4f2) begin
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$fatal(1, "direct Montgomery result mismatch: %h", mont_result);
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end
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@(negedge clk_i);
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mont_left = 64'h9abcdefafa4fa4f2;
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mont_right = 64'h9abcdefafa4fa4f2;
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mont_start = 1'b1;
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@(negedge clk_i);
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mont_start = 1'b0;
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wait (mont_done);
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if (mont_result != 64'hba9c5877ea4e6ea3) begin
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$fatal(1, "direct Montgomery square mismatch: %h", mont_result);
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end
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base_i = 64'h0123456789abcdef;
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exponent_i = 64'h0000000000010001;
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exponent_bits_i = 12'd17;
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pulse_start(1'b0);
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if (result_o != 64'h61c4c4e9f38bdddb) begin
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$fatal(1, "RSA public result mismatch: %h", result_o);
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end
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base_i = 64'h61c4c4e9f38bdddb;
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exponent_i = 64'h81817e725d5da2d9;
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exponent_bits_i = 12'd64;
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pulse_start(1'b1);
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if (result_o != 64'h0123456789abcdef) begin
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$fatal(1, "RSA private result mismatch: %h", result_o);
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end
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@(negedge clk_i);
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zeroize_i = 1'b1;
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@(negedge clk_i);
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zeroize_i = 1'b0;
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if (prepared_o || result_valid_o) begin
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$fatal(1, "RSA zeroize retained prepared or result state");
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end
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$display("Crypto RSA Montgomery tests passed");
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$finish;
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end
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endmodule
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