mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-06 14:55:14 +00:00
maksyuki
98eb8ebad6
- Implemented tests for AXI4 async bridge functionality, including transfer and warm flush scenarios. - Added tests for AXI4 data crossbar to validate concurrent outstanding requests and ACL handling. - Introduced clock frequency monitor tests to ensure detection of clock stop and restart events. - Developed tests for extension DMA master to verify copy operations, tail strobe behavior, and timeout handling. - Created tests for HP lifecycle controller to validate drain, flush, and forced reset functionalities. - Updated existing test scripts to include new RTL components and ensure proper simulation configurations.
126 lines
3.4 KiB
Systemverilog
126 lines
3.4 KiB
Systemverilog
`timescale 1ns / 1ps
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module extension_dma_master_tb;
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logic clk_i = 1'b0;
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logic rst_n_i = 1'b0;
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logic start_i = 1'b0;
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logic abort_i = 1'b0;
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logic quiesce_i = 1'b0;
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logic [31:0] src_addr_i = 32'h3000_0000;
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logic [31:0] dst_addr_i = 32'h3000_0100;
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logic [31:0] len_i = 32'd12;
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logic [31:0] timeout_i = 32'd16;
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logic busy_o;
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logic done_o;
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logic err_o;
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logic [31:0] fault_addr_o;
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axi4_if #(
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.ADDR_WIDTH(32),
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.DATA_WIDTH(64),
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.ID_WIDTH (3),
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.USER_WIDTH(1)
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) axi4 (
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.aclk (clk_i),
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.aresetn(rst_n_i)
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);
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always #5 clk_i = ~clk_i;
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extension_dma_master u_dut (
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.clk_i (clk_i),
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.rst_n_i (rst_n_i),
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.start_i (start_i),
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.abort_i (abort_i),
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.quiesce_i (quiesce_i),
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.src_addr_i (src_addr_i),
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.dst_addr_i (dst_addr_i),
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.len_i (len_i),
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.timeout_i (timeout_i),
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.busy_o (busy_o),
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.done_o (done_o),
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.err_o (err_o),
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.fault_addr_o(fault_addr_o),
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.axi4 (axi4)
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);
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task automatic start_dma;
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begin
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@(negedge clk_i);
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start_i = 1'b1;
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@(negedge clk_i);
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start_i = 1'b0;
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end
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endtask
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task automatic serve_beat(input logic [31:0] expected_src, input logic [31:0] expected_dst,
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input logic [63:0] data, input logic [7:0] expected_strobe);
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begin
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wait (axi4.arvalid);
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if (axi4.araddr != expected_src) $fatal(1, "DMA read address mismatch");
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@(posedge clk_i);
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@(negedge clk_i);
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axi4.rid = 3'd0;
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axi4.rdata = data;
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axi4.rresp = 2'b00;
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axi4.rlast = 1'b1;
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axi4.rvalid = 1'b1;
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do @(posedge clk_i); while (!axi4.rready);
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@(negedge clk_i);
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axi4.rvalid = 1'b0;
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wait (axi4.awvalid);
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if (axi4.awaddr != expected_dst) $fatal(1, "DMA write address mismatch");
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@(posedge clk_i);
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wait (axi4.wvalid);
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if ((axi4.wdata != data) || (axi4.wstrb != expected_strobe) || !axi4.wlast) begin
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$fatal(1, "DMA write data or tail strobe mismatch");
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end
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@(posedge clk_i);
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@(negedge clk_i);
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axi4.bid = 3'd0;
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axi4.bresp = 2'b00;
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axi4.bvalid = 1'b1;
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do @(posedge clk_i); while (!axi4.bready);
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@(negedge clk_i);
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axi4.bvalid = 1'b0;
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end
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endtask
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initial begin
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axi4.awready = 1'b1;
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axi4.wready = 1'b1;
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axi4.bid = '0;
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axi4.bresp = '0;
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axi4.buser = '0;
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axi4.bvalid = 1'b0;
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axi4.arready = 1'b1;
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axi4.rid = '0;
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axi4.rdata = '0;
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axi4.rresp = '0;
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axi4.rlast = 1'b1;
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axi4.ruser = '0;
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axi4.rvalid = 1'b0;
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repeat (2) @(posedge clk_i);
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rst_n_i = 1'b1;
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start_dma();
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serve_beat(32'h3000_0000, 32'h3000_0100, 64'h1122_3344_5566_7788, 8'hFF);
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serve_beat(32'h3000_0008, 32'h3000_0108, 64'hAABB_CCDD_EEFF_0011, 8'h0F);
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wait (done_o);
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if (err_o || busy_o) $fatal(1, "successful DMA copy reported an error");
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@(negedge clk_i);
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timeout_i = 32'd4;
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len_i = 32'd8;
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axi4.arready = 1'b0;
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start_dma();
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wait (done_o);
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if (!err_o || (fault_addr_o != src_addr_i)) begin
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$fatal(1, "DMA no-progress timeout was not attributed to the source address");
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end
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$display("Extension DMA copy, tail strobe, and timeout test passed");
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$finish;
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end
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endmodule
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