mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-06 14:55:14 +00:00
maksyuki
d164a562ad
- Introduced and its corresponding testbench to monitor fabric interactions. - Updated to include additional checks for ACL and QoS, enhancing the test coverage. - Modified to include the new fabric monitor file. - Created a new test file to validate the functionality of the fabric monitor. - Updated to integrate the fabric monitor interface. - Adjusted to reflect changes in the AXI4 data crossbar test output. - Enhanced to ensure proper generation of connections for the fabric monitor. - Updated user extension tests to account for new local SRAM and stream definitions.
190 lines
6.7 KiB
Systemverilog
190 lines
6.7 KiB
Systemverilog
`timescale 1ns / 1ps
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module fabric_monitor_tb;
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logic clk_i = 1'b0;
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logic rst_n_i = 1'b0;
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logic [ 7:0] master_read_accept_i = '0;
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logic [ 7:0] master_write_accept_i = '0;
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logic [ 7:0] master_read_beat_i = '0;
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logic [ 7:0] master_write_beat_i = '0;
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logic [ 7:0] master_wait_i = '0;
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logic [ 7:0] master_promotion_i = '0;
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logic [ 7:0][2:0] master_read_outstanding_i = '0;
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logic [ 7:0][2:0] master_write_outstanding_i = '0;
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logic [ 5:0] target_read_accept_i = '0;
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logic [ 5:0] target_write_accept_i = '0;
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logic [ 5:0] target_read_beat_i = '0;
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logic [ 5:0] target_write_beat_i = '0;
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logic [ 5:0] target_wait_i = '0;
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logic [ 5:0] target_timeout_i = '0;
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logic [ 5:0] target_isolated_i = '0;
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logic [ 5:0][2:0] target_read_outstanding_i = '0;
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logic [ 5:0][2:0] target_write_outstanding_i = '0;
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logic fault_valid_i = 1'b0;
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logic [31:0] read_data;
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apb4_if apb4 (
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.pclk (clk_i),
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.presetn(rst_n_i)
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);
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always #5 clk_i = ~clk_i;
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fabric_monitor u_dut (
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.clk_i (clk_i),
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.rst_n_i (rst_n_i),
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.idle_i (1'b0),
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.recovery_i (1'b1),
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.flush_busy_i (1'b0),
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.flush_i (target_timeout_i[5]),
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.outstanding_read_i (8'd2),
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.outstanding_write_i (8'd1),
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.fault_valid_i (fault_valid_i),
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.fault_master_i (3'd5),
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.fault_target_i (3'd2),
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.fault_addr_i (32'h4000_0040),
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.fault_write_i (1'b1),
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.fault_reason_i (4'd5),
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.master_read_accept_i (master_read_accept_i),
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.master_write_accept_i (master_write_accept_i),
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.master_read_beat_i (master_read_beat_i),
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.master_write_beat_i (master_write_beat_i),
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.master_wait_i (master_wait_i),
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.master_promotion_i (master_promotion_i),
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.master_read_outstanding_i (master_read_outstanding_i),
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.master_write_outstanding_i(master_write_outstanding_i),
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.target_read_accept_i (target_read_accept_i),
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.target_write_accept_i (target_write_accept_i),
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.target_read_beat_i (target_read_beat_i),
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.target_write_beat_i (target_write_beat_i),
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.target_wait_i (target_wait_i),
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.target_timeout_i (target_timeout_i),
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.target_isolated_i (target_isolated_i),
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.target_read_outstanding_i (target_read_outstanding_i),
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.target_write_outstanding_i(target_write_outstanding_i),
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.apb4 (apb4)
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);
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task automatic apb_write(input logic [11:0] offset, input logic [31:0] data);
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begin
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@(negedge clk_i);
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apb4.paddr = {20'd0, offset};
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apb4.pwrite = 1'b1;
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apb4.pwdata = data;
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apb4.pstrb = 4'hF;
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apb4.psel = 1'b1;
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apb4.penable = 1'b1;
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do @(posedge clk_i); while (!apb4.pready);
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if (apb4.pslverr) $fatal(1, "fabric monitor write failed at %h", offset);
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@(negedge clk_i);
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apb4.psel = 1'b0;
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apb4.penable = 1'b0;
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apb4.pwrite = 1'b0;
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apb4.pstrb = '0;
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end
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endtask
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task automatic apb_read(input logic [11:0] offset, output logic [31:0] data);
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begin
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@(negedge clk_i);
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apb4.paddr = {20'd0, offset};
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apb4.pwrite = 1'b0;
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apb4.pstrb = '0;
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apb4.psel = 1'b1;
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apb4.penable = 1'b1;
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do @(posedge clk_i); while (!apb4.pready);
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if (apb4.pslverr) $fatal(1, "fabric monitor read failed at %h", offset);
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data = apb4.prdata;
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@(negedge clk_i);
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apb4.psel = 1'b0;
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apb4.penable = 1'b0;
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end
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endtask
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initial begin
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apb4.paddr = '0;
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apb4.pprot = '0;
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apb4.psel = 1'b0;
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apb4.penable = 1'b0;
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apb4.pwrite = 1'b0;
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apb4.pwdata = '0;
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apb4.pstrb = '0;
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repeat (3) @(posedge clk_i);
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rst_n_i = 1'b1;
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apb_write(12'h00C, 32'h0000_0001);
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@(negedge clk_i);
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master_read_accept_i[0] = 1'b1;
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master_read_beat_i[0] = 1'b1;
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master_promotion_i[0] = 1'b1;
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master_read_outstanding_i[0] = 3'd3;
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target_read_accept_i[2] = 1'b1;
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target_read_beat_i[2] = 1'b1;
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target_read_outstanding_i[2] = 3'd2;
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@(negedge clk_i);
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master_read_accept_i = '0;
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master_read_beat_i = '0;
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master_promotion_i = '0;
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target_read_accept_i = '0;
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target_read_beat_i = '0;
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repeat (3) begin
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master_wait_i[0] = 1'b1;
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target_wait_i[2] = 1'b1;
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@(negedge clk_i);
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end
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master_wait_i = '0;
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target_wait_i = '0;
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target_timeout_i[2] = 1'b1;
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target_isolated_i[2] = 1'b1;
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fault_valid_i = 1'b1;
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@(negedge clk_i);
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target_timeout_i[2] = 1'b0;
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fault_valid_i = 1'b0;
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target_timeout_i[5] = 1'b1;
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@(negedge clk_i);
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target_timeout_i[5] = 1'b0;
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apb_write(12'h00C, 32'h0000_0009);
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apb_read(12'h100, read_data);
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if (read_data != 32'd1) $fatal(1, "master read request count mismatch");
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apb_read(12'h110, read_data);
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if (read_data != 32'd3) $fatal(1, "master wait count mismatch");
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apb_read(12'h114, read_data);
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if (read_data != 32'd3) $fatal(1, "master max wait mismatch");
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apb_read(12'h118, read_data);
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if (read_data != 32'd1) $fatal(1, "master promotion count mismatch");
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apb_read(12'h11C, read_data);
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if (read_data[2:0] != 3'd3) $fatal(1, "master high-water mismatch");
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apb_read(12'h340, read_data);
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if (read_data != 32'd1) $fatal(1, "target read request count mismatch");
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apb_read(12'h350, read_data);
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if (read_data != 32'd3) $fatal(1, "target wait count mismatch");
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apb_read(12'h354, read_data);
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if (read_data != 32'd1) $fatal(1, "target timeout count mismatch");
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apb_read(12'h358, read_data);
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if (read_data != 32'd1) $fatal(1, "target isolation mismatch");
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apb_read(12'h01C, read_data);
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if (read_data != 32'd1) $fatal(1, "flush count mismatch");
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apb_read(12'h018, read_data);
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if (read_data != 32'h4000_0040) $fatal(1, "fault address mismatch");
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apb_read(12'h014, read_data);
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if (read_data != 32'h0000_0557) $fatal(1, "sticky fault attribution mismatch");
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apb_read(12'h020, read_data);
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if (read_data != 32'd1) $fatal(1, "fault count mismatch");
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apb_write(12'h00C, 32'h0000_0005);
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apb_read(12'h100, read_data);
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if (read_data != 32'd0) $fatal(1, "snapshot did not clear");
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apb_read(12'h014, read_data);
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if (read_data != 32'd0) $fatal(1, "sticky fault did not clear");
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$display("Fabric Monitor counter, snapshot, and clear test passed");
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$finish;
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end
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initial begin
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repeat (400) @(posedge clk_i);
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$fatal(1, "Fabric Monitor test timed out");
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end
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endmodule
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