mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-06 14:55:14 +00:00
maksyuki
d164a562ad
- Introduced and its corresponding testbench to monitor fabric interactions. - Updated to include additional checks for ACL and QoS, enhancing the test coverage. - Modified to include the new fabric monitor file. - Created a new test file to validate the functionality of the fabric monitor. - Updated to integrate the fabric monitor interface. - Adjusted to reflect changes in the AXI4 data crossbar test output. - Enhanced to ensure proper generation of connections for the fabric monitor. - Updated user extension tests to account for new local SRAM and stream definitions.
208 lines
6.3 KiB
Systemverilog
208 lines
6.3 KiB
Systemverilog
`timescale 1ns / 1ps
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`include "rib_defs.svh"
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module rib2apb_tb;
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logic clk_i = 1'b0;
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logic rst_n_i = 1'b0;
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logic rng_ready = 1'b0;
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logic rng_slverr = 1'b0;
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logic [31:0] rng_rdata = 32'h1234_5678;
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rib_if rib ();
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apb4_pure_if archinfo ();
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apb4_pure_if rng ();
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apb4_pure_if pwm ();
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apb4_pure_if ps2 ();
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apb4_pure_if rtc ();
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apb4_pure_if wdg ();
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apb4_pure_if crc ();
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apb4_pure_if user_ip ();
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apb4_pure_if ext_l ();
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apb4_pure_if ext_h ();
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apb4_pure_if resource_ctrl ();
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apb4_pure_if fabric_monitor ();
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always #5 clk_i = ~clk_i;
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assign archinfo.pready = 1'b0;
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assign archinfo.prdata = '0;
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assign archinfo.pslverr = 1'b0;
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assign rng.pready = rng_ready;
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assign rng.prdata = rng_rdata;
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assign rng.pslverr = rng_slverr;
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assign pwm.pready = 1'b0;
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assign pwm.prdata = '0;
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assign pwm.pslverr = 1'b0;
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assign ps2.pready = 1'b0;
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assign ps2.prdata = '0;
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assign ps2.pslverr = 1'b0;
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assign rtc.pready = 1'b0;
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assign rtc.prdata = '0;
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assign rtc.pslverr = 1'b0;
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assign wdg.pready = 1'b0;
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assign wdg.prdata = '0;
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assign wdg.pslverr = 1'b0;
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assign crc.pready = 1'b0;
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assign crc.prdata = '0;
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assign crc.pslverr = 1'b0;
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assign user_ip.pready = 1'b0;
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assign user_ip.prdata = '0;
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assign user_ip.pslverr = 1'b0;
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assign ext_l.pready = 1'b0;
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assign ext_l.prdata = '0;
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assign ext_l.pslverr = 1'b0;
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assign ext_h.pready = 1'b0;
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assign ext_h.prdata = '0;
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assign ext_h.pslverr = 1'b0;
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assign resource_ctrl.pready = 1'b0;
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assign resource_ctrl.prdata = '0;
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assign resource_ctrl.pslverr = 1'b0;
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assign fabric_monitor.pready = 1'b0;
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assign fabric_monitor.prdata = '0;
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assign fabric_monitor.pslverr = 1'b0;
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rib2apb u_rib2apb (
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.clk_i (clk_i),
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.rst_n_i (rst_n_i),
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.rib (rib),
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.archinfo (archinfo),
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.rng (rng),
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.pwm (pwm),
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.ps2 (ps2),
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.rtc (rtc),
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.wdg (wdg),
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.crc (crc),
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.user_ip (user_ip),
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.ext_l (ext_l),
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.ext_h (ext_h),
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.resource_ctrl (resource_ctrl),
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.fabric_monitor(fabric_monitor)
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);
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task automatic send_command(input logic [31:0] address, input logic write,
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input logic [1:0] length);
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begin
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@(negedge clk_i);
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rib.cmd_addr = address;
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rib.cmd_write = write;
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rib.cmd_len = length;
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rib.cmd_valid = 1'b1;
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while (!rib.cmd_ready) @(posedge clk_i);
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@(negedge clk_i);
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rib.cmd_valid = 1'b0;
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end
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endtask
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task automatic send_write(input logic [31:0] data, input logic [3:0] strobes, input logic last);
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begin
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@(negedge clk_i);
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rib.wdata = data;
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rib.wstrb = strobes;
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rib.wlast = last;
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rib.w_valid = 1'b1;
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while (!rib.w_ready) @(posedge clk_i);
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@(negedge clk_i);
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rib.w_valid = 1'b0;
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end
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endtask
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task automatic wait_for_rng_enable;
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begin
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while (!(rng.psel && rng.penable)) @(posedge clk_i);
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end
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endtask
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task automatic expect_response(input logic expected_error, input logic [2:0] expected_code,
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input logic [31:0] expected_data);
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begin
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while (!rib.rsp_valid) @(posedge clk_i);
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#1;
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if (rib.resp_err !== expected_error || rib.resp_code !== expected_code ||
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rib.rdata !== expected_data || rib.rsp_beat !== 2'd0 || !rib.rsp_last) begin
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$fatal(1, "unexpected RIB response error=%b/%b code=%0d/%0d data=%h/%h fsm=%0d",
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rib.resp_err, expected_error, rib.resp_code, expected_code, rib.rdata,
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expected_data, u_rib2apb.s_fsm_q);
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end
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end
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endtask
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initial begin
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rib.cmd_valid = 1'b0;
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rib.cmd_addr = '0;
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rib.cmd_write = 1'b0;
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rib.cmd_len = `RIB_LEN_INCR1;
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rib.w_valid = 1'b0;
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rib.wdata = '0;
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rib.wstrb = '0;
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rib.wlast = 1'b0;
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rib.rsp_ready = 1'b1;
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repeat (2) @(posedge clk_i);
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rst_n_i = 1'b1;
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send_command(32'h2000_1000, 1'b0, `RIB_LEN_INCR1);
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while (!(rng.psel && !rng.penable)) @(posedge clk_i);
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wait_for_rng_enable();
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if (rng.paddr !== 32'h2000_1000 || rng.pwrite || rng.pstrb !== 4'd0) begin
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$fatal(1, "read APB setup was not held from the RIB command");
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end
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repeat (2) begin
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@(posedge clk_i);
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if (!(rng.psel && rng.penable) || rng.paddr !== 32'h2000_1000) begin
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$fatal(1, "APB read request changed while PREADY was low");
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end
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end
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rib.rsp_ready = 1'b0;
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@(negedge clk_i);
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rng_ready = 1'b1;
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expect_response(1'b0, `RIB_RESP_OK, 32'h1234_5678);
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repeat (2) begin
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@(posedge clk_i);
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if (!rib.rsp_valid || rib.rdata !== 32'h1234_5678) begin
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$fatal(1, "response did not remain stable under RIB backpressure");
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end
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end
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rib.rsp_ready = 1'b1;
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@(posedge clk_i);
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@(negedge clk_i);
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rng_ready = 1'b0;
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send_command(32'h2000_1000, 1'b1, `RIB_LEN_INCR1);
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send_write(32'hA5A5_5A5A, 4'hC, 1'b1);
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wait_for_rng_enable();
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if (!rng.pwrite || rng.pwdata !== 32'hA5A5_5A5A || rng.pstrb !== 4'hC) begin
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$fatal(1, "APB write data was not held from the RIB write channel");
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end
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@(negedge clk_i);
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rng_ready = 1'b1;
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expect_response(1'b0, `RIB_RESP_OK, 32'd0);
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@(posedge clk_i);
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@(negedge clk_i);
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rng_ready = 1'b0;
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rng_slverr = 1'b1;
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send_command(32'h2000_1000, 1'b0, `RIB_LEN_INCR1);
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wait_for_rng_enable();
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@(negedge clk_i);
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rng_ready = 1'b1;
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expect_response(1'b1, `RIB_RESP_SLVERR, 32'h1234_5678);
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@(posedge clk_i);
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@(negedge clk_i);
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rng_ready = 1'b0;
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rng_slverr = 1'b0;
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send_command(32'h2000_1000, 1'b1, `RIB_LEN_INCR4);
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send_write(32'h0000_0001, 4'hF, 1'b0);
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send_write(32'h0000_0002, 4'hF, 1'b0);
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send_write(32'h0000_0003, 4'hF, 1'b0);
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send_write(32'h0000_0004, 4'hF, 1'b1);
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if (rng.psel) $fatal(1, "illegal RIB burst reached the APB target");
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expect_response(1'b1, `RIB_RESP_BURSTERR, 32'd0);
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@(posedge clk_i);
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$display("RIB2APB direct bridge test passed");
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$finish;
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end
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endmodule
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