mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-06 14:55:14 +00:00
maksyuki
a8325ab6b7
- Introduced a new testbench for the SDIO wrapper () to validate APB interactions. - Updated to include IRQ handling for SDIO0 and SDIO1. - Enhanced to account for performance management of SDIO0 and SDIO1. - Modified memory map tests to include SDIO base addresses and performance wait offsets. - Updated pin mapping tests to include SDIO1 signals. - Created a comprehensive suite of SDIO tests () covering various functionalities including CRC, command engine, DMA, and standalone operations. - Added a new test for verifying SDIO register parity against the RTL definition. - Adjusted SOC topology tests to reflect the addition of SDIO in the IRQ and APB fabric.
67 lines
1.4 KiB
Systemverilog
67 lines
1.4 KiB
Systemverilog
`timescale 1ns / 1ps
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module sdio_crc_tb;
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logic [39:0] crc7_data;
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logic [ 6:0] crc7_value;
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logic [15:0] crc16_value;
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logic [15:0] crc16_seed;
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logic [ 7:0] crc16_data;
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sdio_crc7 u_sdio_crc7 (
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.data_i(crc7_data),
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.crc_o (crc7_value)
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);
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sdio_crc16 u_sdio_crc16 (
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.crc_i (crc16_seed),
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.data_i(crc16_data),
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.crc_o (crc16_value)
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);
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initial begin
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crc7_data = {1'b0, 1'b1, 6'd0, 32'd0};
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#1;
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if (crc7_value != 7'h4A) begin
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$fatal(1, "CMD0 CRC7 mismatch: %h", crc7_value);
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end
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crc7_data = {1'b0, 1'b1, 6'd8, 32'h0000_01AA};
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#1;
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if (crc7_value != 7'h43) begin
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$fatal(1, "CMD8 CRC7 mismatch: %h", crc7_value);
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end
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crc16_seed = 16'h0000;
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crc16_data = "1";
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#1;
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crc16_seed = crc16_value;
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crc16_data = "2";
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#1;
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crc16_seed = crc16_value;
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crc16_data = "3";
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#1;
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crc16_seed = crc16_value;
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crc16_data = "4";
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#1;
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crc16_seed = crc16_value;
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crc16_data = "5";
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#1;
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crc16_seed = crc16_value;
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crc16_data = "6";
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#1;
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crc16_seed = crc16_value;
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crc16_data = "7";
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#1;
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crc16_seed = crc16_value;
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crc16_data = "8";
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#1;
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crc16_seed = crc16_value;
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crc16_data = "9";
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#1;
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if (crc16_value != 16'h31C3) begin
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$fatal(1, "CRC16 mismatch: %h", crc16_value);
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end
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$display("SDIO CRC vectors passed");
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$finish;
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end
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endmodule
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