mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-06 14:55:14 +00:00
maksyuki
a8325ab6b7
- Introduced a new testbench for the SDIO wrapper () to validate APB interactions. - Updated to include IRQ handling for SDIO0 and SDIO1. - Enhanced to account for performance management of SDIO0 and SDIO1. - Modified memory map tests to include SDIO base addresses and performance wait offsets. - Updated pin mapping tests to include SDIO1 signals. - Created a comprehensive suite of SDIO tests () covering various functionalities including CRC, command engine, DMA, and standalone operations. - Added a new test for verifying SDIO register parity against the RTL definition. - Adjusted SOC topology tests to reflect the addition of SDIO in the IRQ and APB fabric.
343 lines
11 KiB
Systemverilog
343 lines
11 KiB
Systemverilog
// Copyright (c) 2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
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// retroSoC is licensed under Mulan PSL v2.
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// You can use this software according to the terms and conditions of the Mulan PSL v2.
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// You may obtain a copy of the Mulan PSL v2 at:
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// http://license.coscl.org.cn/MulanPSL2
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// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
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// INCLUDING, BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A
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// PARTICULAR PURPOSE.
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// See the Mulan PSL v2 for more details.
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`timescale 1ns / 1ps
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module sdio_sdio_tb;
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localparam logic [31:0] HostCtrl = 32'h00C;
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localparam logic [31:0] ClockCtrl = 32'h010;
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localparam logic [31:0] BusCtrl = 32'h018;
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localparam logic [31:0] CmdArg = 32'h040;
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localparam logic [31:0] CmdCfg = 32'h044;
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localparam logic [31:0] CmdStart = 32'h048;
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localparam logic [31:0] CmdStatus = 32'h04C;
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localparam logic [31:0] Resp0 = 32'h050;
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localparam logic [31:0] BlockSize = 32'h080;
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localparam logic [31:0] BlockCount = 32'h084;
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localparam logic [31:0] DataCfg = 32'h088;
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localparam logic [31:0] DataStart = 32'h08C;
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localparam logic [31:0] PioData = 32'h090;
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localparam logic [31:0] IrqStatus = 32'h100;
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localparam logic [31:0] IrqEnable = 32'h104;
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logic clk_i = 1'b0;
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logic rst_n_i = 1'b0;
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apb4_if apb4 (
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.pclk (clk_i),
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.presetn(rst_n_i)
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);
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axi4_if #(
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.ADDR_WIDTH(32),
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.DATA_WIDTH(32),
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.ID_WIDTH (1),
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.USER_WIDTH(1)
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) dma_axi4 (
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.aclk (clk_i),
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.aresetn(rst_n_i)
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);
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sdio_if sdio ();
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logic card_cmd_do;
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logic [ 3:0] card_dat_do;
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logic card_irq;
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logic [31:0] apb_value;
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integer timeout_guard;
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assign sdio.cmd_di_i = sdio.cmd_oe_o ? sdio.cmd_do_o : card_cmd_do;
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assign sdio.dat_di_i = (sdio.dat_oe_o & sdio.dat_do_o) | (~sdio.dat_oe_o & card_dat_do);
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always #5 clk_i = ~clk_i;
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apb4_sdio #(
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.InputClockHz(72_000_000),
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.AddrWidth (32),
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.DataWidth (32),
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.DescCount (16)
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) u_apb4_sdio (
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.clk_i (clk_i),
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.rst_n_i (rst_n_i),
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.apb4 (apb4),
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.dma_axi4(dma_axi4),
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.sdio (sdio)
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);
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sdio_sdio_model #(
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.FunctionCount(2),
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.FunctionBytes(4096),
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.BusyCycles (8)
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) u_card (
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.rst_n_i (rst_n_i),
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.sck_i (sdio.sck_o),
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.cmd_oe_i(sdio.cmd_oe_o),
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.cmd_do_i(sdio.cmd_do_o),
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.cmd_do_o(card_cmd_do),
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.dat_oe_i(sdio.dat_oe_o),
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.dat_do_i(sdio.dat_do_o),
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.dat_do_o(card_dat_do),
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.irq_o (card_irq)
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);
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sdio_axi_memory_responder u_axi_memory (
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.clk_i (clk_i),
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.rst_n_i(rst_n_i),
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.axi4 (dma_axi4)
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);
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task automatic apb_idle;
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begin
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apb4.psel = 1'b0;
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apb4.penable = 1'b0;
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apb4.pwrite = 1'b0;
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apb4.paddr = '0;
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apb4.pwdata = '0;
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apb4.pstrb = '0;
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end
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endtask
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task automatic issue_command_unchecked(input logic [5:0] index_i, input logic [31:0] argument_i,
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input logic [3:0] response_i);
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begin
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apb_write(CmdArg, argument_i, 4'hF);
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apb_write(CmdCfg, {18'd0, 1'b0, 1'b0, response_i, 2'd0, index_i}, 4'hF);
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apb_write(CmdStart, 32'd1, 4'h1);
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wait_command();
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end
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endtask
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task automatic apb_write(input logic [31:0] address_i, input logic [31:0] data_i,
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input logic [3:0] strobe_i);
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begin
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@(negedge clk_i);
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apb4.paddr = address_i;
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apb4.pwdata = data_i;
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apb4.pstrb = strobe_i;
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apb4.pwrite = 1'b1;
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apb4.psel = 1'b1;
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apb4.penable = 1'b0;
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@(negedge clk_i);
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apb4.penable = 1'b1;
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@(posedge clk_i);
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#1;
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if (!apb4.pready || apb4.pslverr) begin
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$fatal(1, "SDIO APB write failed addr=%h data=%h", address_i, data_i);
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end
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apb_idle();
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end
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endtask
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task automatic apb_read(input logic [31:0] address_i, output logic [31:0] data_o);
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begin
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@(negedge clk_i);
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apb4.paddr = address_i;
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apb4.pwdata = '0;
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apb4.pstrb = '0;
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apb4.pwrite = 1'b0;
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apb4.psel = 1'b1;
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apb4.penable = 1'b0;
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@(negedge clk_i);
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apb4.penable = 1'b1;
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@(posedge clk_i);
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#1;
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if (!apb4.pready || apb4.pslverr) begin
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$fatal(1, "SDIO APB read failed addr=%h", address_i);
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end
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data_o = apb4.prdata;
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apb_idle();
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end
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endtask
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task automatic wait_command;
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logic seen_busy;
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begin
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timeout_guard = 0;
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seen_busy = 1'b0;
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while (timeout_guard < 20000) begin
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@(posedge clk_i);
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timeout_guard = timeout_guard + 1;
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if (u_apb4_sdio.u_sdio_core.s_cmd_busy) begin
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seen_busy = 1'b1;
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end
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if (seen_busy && (u_apb4_sdio.u_sdio_core.u_sdio_command.s_state_q == 3'd0)) begin
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break;
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end
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end
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if (timeout_guard >= 20000) begin
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$fatal(1, "SDIO command did not drain");
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end
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end
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endtask
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task automatic wait_data;
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logic seen_busy;
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begin
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timeout_guard = 0;
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seen_busy = 1'b0;
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while (timeout_guard < 200000) begin
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@(posedge clk_i);
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timeout_guard = timeout_guard + 1;
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if (u_apb4_sdio.u_sdio_core.s_data_busy || u_apb4_sdio.u_sdio_core.s_dma_busy) begin
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seen_busy = 1'b1;
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end
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if (seen_busy && !u_apb4_sdio.u_sdio_core.s_data_busy &&
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!u_apb4_sdio.u_sdio_core.s_dma_busy) begin
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break;
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end
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end
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if (timeout_guard >= 200000) begin
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$fatal(1, "SDIO data path did not drain");
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end
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end
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endtask
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task automatic wait_write_ready;
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begin
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timeout_guard = 0;
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while ((u_apb4_sdio.u_sdio_core.u_sdio_data.s_state_q != 4'd1) &&
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(timeout_guard < 1000)) begin
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@(posedge clk_i);
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timeout_guard = timeout_guard + 1;
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end
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if (timeout_guard >= 1000) begin
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$fatal(1, "SDIO write engine did not become ready");
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end
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end
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endtask
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task automatic issue_command(input logic [5:0] index_i, input logic [31:0] argument_i,
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input logic [3:0] response_i);
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logic [31:0] status_value;
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begin
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apb_write(CmdArg, argument_i, 4'hF);
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apb_write(CmdCfg, {18'd0, 1'b1, 1'b1, response_i, 2'd0, index_i}, 4'hF);
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apb_write(CmdStart, 32'd1, 4'h1);
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wait_command();
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apb_read(CmdStatus, status_value);
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if ((status_value & 32'h0000_001E) != 0) begin
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$fatal(1, "SDIO command %0d failed status=%h", index_i, status_value);
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end
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end
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endtask
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task automatic configure_data(input logic width4_i, input logic direction_i,
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input logic block_mode_i, input logic fixed_address_i,
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input logic [15:0] bytes_i, input logic [15:0] count_i);
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begin
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apb_write(BusCtrl, width4_i ? 32'd1 : 32'd0, 4'h1);
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apb_write(BlockSize, {16'd0, bytes_i}, 4'hF);
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apb_write(BlockCount, {16'd0, count_i}, 4'hF);
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apb_write(DataCfg, {
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25'd0, fixed_address_i, block_mode_i, 1'b0, 1'b0, 1'b0, width4_i, direction_i},
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4'h1);
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end
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endtask
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initial begin
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apb_idle();
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repeat (4) @(posedge clk_i);
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rst_n_i = 1'b1;
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apb_write(ClockCtrl, 32'h0000_0101, 4'hF);
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apb_write(HostCtrl, 32'h0000_0005, 4'h1);
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// SDIO enumeration and CCCR/FBR/CIS-backed direct accesses.
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issue_command(6'd5, 32'h0000_0000, 4'd5);
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repeat (8) @(posedge clk_i);
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issue_command(6'd52, 32'h0000_0000, 4'd6);
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apb_read(Resp0, apb_value);
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if (apb_value[15:8] != 8'h03) begin
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$fatal(1, "CCCR version mismatch: %h", apb_value);
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end
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issue_command(6'd52, {1'b0, 3'd0, 1'b0, 1'b0, 17'h00013, 1'b0, 8'h00}, 4'd6);
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apb_read(Resp0, apb_value);
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if (apb_value[15:8] != 8'h01) $fatal(1, "CCCR high-speed capability missing");
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issue_command(6'd52, {1'b1, 3'd0, 1'b0, 1'b0, 17'h00013, 1'b0, 8'h03}, 4'd6);
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issue_command(6'd52, {1'b0, 3'd0, 1'b0, 1'b0, 17'h00013, 1'b0, 8'h00}, 4'd6);
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apb_read(Resp0, apb_value);
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if (apb_value[15:8] != 8'h03) $fatal(1, "CCCR high-speed enable did not stick");
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issue_command(6'd52, {1'b1, 3'd0, 1'b0, 1'b0, 17'h00004, 1'b0, 8'h5A}, 4'd6);
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apb_read(Resp0, apb_value);
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if (apb_value[15:8] != 8'h5A) begin
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$fatal(1, "CCCR write response mismatch: %h", apb_value);
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end
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// CMD53 byte mode, incrementing address, 4-bit SDR.
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issue_command_unchecked(6'd53, {1'b0, 3'd1, 1'b0, 1'b1, 17'h00020, 9'd4}, 4'd0);
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configure_data(1'b1, 1'b0, 1'b0, 1'b0, 16'd4, 16'd1);
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u_card.arm_read(4096 + 32, 4, 1'b1, 1'b0);
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apb_write(DataStart, 32'd1, 4'h1);
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wait_data();
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apb_read(PioData, apb_value);
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if (apb_value != 32'h0000_0000) begin
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$fatal(1, "unexpected initial function memory: %h", apb_value);
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end
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// CMD53 block mode, fixed address, 1-bit SDR write.
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issue_command_unchecked(6'd53, {1'b1, 3'd1, 1'b1, 1'b0, 17'h00030, 9'd1}, 4'd0);
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configure_data(1'b0, 1'b1, 1'b1, 1'b1, 16'd4, 16'd1);
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u_card.arm_write(4096 + 48, 4, 1'b0, 1'b1);
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apb_write(DataStart, 32'd1, 4'h1);
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wait_write_ready();
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apb_write(PioData, 32'h1122_3344, 4'hF);
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wait_data();
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if (u_card.read_backing(4096 + 48) != 8'h11) begin
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$fatal(1, "fixed-address CMD53 write did not land: %h", u_card.read_backing(4096 + 48));
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end
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apb_write(IrqEnable, 32'h0000_0040, 4'h1);
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apb_write(IrqStatus, 32'h0000_00FF, 4'h1);
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u_card.clear_irq();
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repeat (4) @(posedge clk_i);
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apb_read(IrqStatus, apb_value);
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if ((apb_value & 32'h0000_0040) != 0 || sdio.irq_o) begin
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$fatal(1, "DAT1 high level caused a false host IRQ");
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end
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// DAT1 is an active-low function interrupt. It is synchronized in clk_i,
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// qualified only while the host releases the data path, and remains sticky
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// while SDCLK is stopped.
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u_card.set_irq();
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repeat (4) @(posedge clk_i);
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if (sdio.dat_di_i[1] != 1'b0 || !card_irq) begin
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$fatal(1, "SDIO DAT1 interrupt was not asserted low");
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end
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apb_read(IrqStatus, apb_value);
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if ((apb_value & 32'h0000_0040) == 0 || !sdio.irq_o) begin
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$fatal(1, "active-low DAT1 did not latch host IRQ");
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end
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apb_write(IrqStatus, 32'h0000_0040, 4'h1);
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repeat (8) @(posedge clk_i);
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apb_read(IrqStatus, apb_value);
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if ((apb_value & 32'h0000_0040) != 0 || sdio.irq_o) begin
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$fatal(1, "DAT1 W1C did not clear sticky host IRQ");
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end
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if (sdio.sck_o != 1'b0) begin
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$fatal(1, "SDCLK was not stopped for DAT1 persistence check");
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end
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repeat (8) @(posedge clk_i);
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apb_read(IrqStatus, apb_value);
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if ((apb_value & 32'h0000_0040) != 0) begin
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$fatal(1, "cleared DAT1 IRQ reasserted while line remained low");
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end
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u_card.clear_irq();
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repeat (4) @(posedge clk_i);
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if (sdio.dat_di_i[1] != 1'b1) begin
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$fatal(1, "DAT1 interrupt did not release");
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end
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u_card.set_irq();
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repeat (4) @(posedge clk_i);
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apb_read(IrqStatus, apb_value);
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if ((apb_value & 32'h0000_0040) == 0) begin
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$fatal(1, "DAT1 did not re-arm after returning high");
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end
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$display("SDIO-only CMD5/CMD52/CMD53/DAT1 test passed");
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$finish;
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end
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endmodule
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