mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-06 14:55:14 +00:00
maksyuki
a8325ab6b7
- Introduced a new testbench for the SDIO wrapper () to validate APB interactions. - Updated to include IRQ handling for SDIO0 and SDIO1. - Enhanced to account for performance management of SDIO0 and SDIO1. - Modified memory map tests to include SDIO base addresses and performance wait offsets. - Updated pin mapping tests to include SDIO1 signals. - Created a comprehensive suite of SDIO tests () covering various functionalities including CRC, command engine, DMA, and standalone operations. - Added a new test for verifying SDIO register parity against the RTL definition. - Adjusted SOC topology tests to reflect the addition of SDIO in the IRQ and APB fabric.
75 lines
1.7 KiB
Systemverilog
75 lines
1.7 KiB
Systemverilog
`timescale 1ns / 1ps
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`include "axi4_define.svh"
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module sdio_wrapper_tb;
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logic clk_i = 1'b0;
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logic rst_n_i = 1'b0;
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apb4_if apb4 (
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.pclk (clk_i),
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.presetn(rst_n_i)
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);
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axi4_if #(
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.ADDR_WIDTH(32),
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.DATA_WIDTH(32),
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.ID_WIDTH (1),
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.USER_WIDTH(1)
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) dma_axi4 (
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.aclk (clk_i),
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.aresetn(rst_n_i)
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);
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sdio_if sdio ();
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always #5 clk_i = ~clk_i;
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assign dma_axi4.awready = 1'b1;
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assign dma_axi4.wready = 1'b1;
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assign dma_axi4.bid = '0;
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assign dma_axi4.bresp = `AXI4_RESP_OKAY;
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assign dma_axi4.buser = '0;
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assign dma_axi4.bvalid = 1'b0;
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assign dma_axi4.arready = 1'b1;
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assign dma_axi4.rid = '0;
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assign dma_axi4.rdata = '0;
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assign dma_axi4.rresp = `AXI4_RESP_OKAY;
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assign dma_axi4.rlast = 1'b1;
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assign dma_axi4.ruser = '0;
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assign dma_axi4.rvalid = 1'b0;
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apb4_sdio #(
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.InputClockHz(72_000_000),
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.AddrWidth (32),
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.DataWidth (32),
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.DescCount (16)
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) u_apb4_sdio (
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.clk_i (clk_i),
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.rst_n_i (rst_n_i),
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.apb4 (apb4),
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.dma_axi4(dma_axi4),
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.sdio (sdio)
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);
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initial begin
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apb4.paddr = '0;
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apb4.pprot = '0;
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apb4.psel = 1'b0;
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apb4.penable = 1'b0;
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apb4.pwrite = 1'b0;
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apb4.pwdata = '0;
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apb4.pstrb = '0;
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repeat (3) @(posedge clk_i);
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rst_n_i = 1'b1;
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@(negedge clk_i);
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apb4.paddr = 32'h0000_0000;
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apb4.psel = 1'b1;
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@(negedge clk_i);
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apb4.penable = 1'b1;
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@(posedge clk_i);
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#1;
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if (!apb4.pready || apb4.pslverr || (apb4.prdata != 32'h5344_494F)) begin
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$fatal(1, "wrapper APB identification failed");
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end
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$display("SDIO wrapper elaboration and APB smoke test passed");
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$finish;
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end
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endmodule
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