mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-06 14:55:14 +00:00
maksyuki
a32d9af957
- Introduced burst length handling in the SDRAM Verilator model, allowing for more flexible read/write operations. - Added new SDRAM-related source files to the project structure, including sdram_pkg.sv and sdram_axi4.sv. - Updated software makefile to include new SDRAM-related C source files for HAL. - Enhanced C test suite with new tests for SDRAM timing and functionality, ensuring proper integration with the HAL. - Improved RTL testbench for SDRAM, adding support for burst writes and reads, and verifying data integrity. - Updated Python test scripts to reflect changes in SDRAM handling and ensure comprehensive coverage of SDRAM functionality. - Added checks to ensure register offsets between RTL and HAL definitions match, maintaining consistency across the codebase.
372 lines
11 KiB
Systemverilog
372 lines
11 KiB
Systemverilog
`timescale 1ns / 1ps
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`include "axi4_define.svh"
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`include "sdram_define.svh"
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module sdram_data_tb;
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logic clk_i = 1'b0;
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logic rst_n_i = 1'b0;
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wire [15:0] s_dq;
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logic [31:0] s_read_data;
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logic [31:0] s_apb_data;
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axi4_if #(
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.ADDR_WIDTH(32),
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.DATA_WIDTH(32),
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.ID_WIDTH (1),
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.USER_WIDTH(1)
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) axi4 (
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.aclk (clk_i),
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.aresetn(rst_n_i)
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);
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apb4_if cfg_apb4 (
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.pclk (clk_i),
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.presetn(rst_n_i)
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);
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sdram_if sdram ();
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always #5 clk_i = ~clk_i;
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assign s_dq = sdram.oe_o ? sdram.dq_o : 'z;
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assign sdram.dq_i = s_dq;
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axi4_sdram u_axi4_sdram (
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.clk_i (clk_i),
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.rst_n_i (rst_n_i),
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.axi4 (axi4),
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.cfg_apb4(cfg_apb4),
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.sdram (sdram)
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);
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`ifdef SDRAM_TIMING_MODEL
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sdr u_sdr (
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.Clk (sdram.clk_o),
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.Cke (sdram.cke_o),
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.Cs_n (sdram.cs_n_o),
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.Ras_n(sdram.ras_n_o),
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.Cas_n(sdram.cas_n_o),
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.We_n (sdram.we_n_o),
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.Addr (sdram.addr_o),
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.Ba (sdram.ba_o),
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.Dq (s_dq),
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.Dqm (sdram.dqm_o)
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);
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`else
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sdram_verilator_model u_sdram_verilator_model (
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.clk_i (sdram.clk_o),
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.cke_i (sdram.cke_o),
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.cs_n_i (sdram.cs_n_o),
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.ras_n_i(sdram.ras_n_o),
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.cas_n_i(sdram.cas_n_o),
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.we_n_i (sdram.we_n_o),
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.ba_i (sdram.ba_o),
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.addr_i (sdram.addr_o),
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.dqm_i (sdram.dqm_o),
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.dq_io (s_dq)
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);
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`endif
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task automatic init_axi4;
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begin
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axi4.awid = '0;
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axi4.awaddr = '0;
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axi4.awlen = '0;
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axi4.awsize = `AXI4_BURST_SIZE_4BYTES;
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axi4.awburst = `AXI4_BURST_TYPE_INCR;
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axi4.awlock = `AXI4_LOCK_NORM;
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axi4.awcache = `AXI4_CACHE_NO_BUF;
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axi4.awprot = `AXI4_PROT_DATA;
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axi4.awqos = `AXI4_QOS_NORMAL;
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axi4.awregion = `AXI4_REGION_NORMAL;
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axi4.awuser = '0;
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axi4.awvalid = 1'b0;
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axi4.wdata = '0;
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axi4.wstrb = '0;
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axi4.wlast = 1'b0;
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axi4.wuser = '0;
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axi4.wvalid = 1'b0;
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axi4.bready = 1'b0;
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axi4.arid = '0;
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axi4.araddr = '0;
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axi4.arlen = '0;
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axi4.arsize = `AXI4_BURST_SIZE_4BYTES;
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axi4.arburst = `AXI4_BURST_TYPE_INCR;
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axi4.arlock = `AXI4_LOCK_NORM;
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axi4.arcache = `AXI4_CACHE_NO_BUF;
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axi4.arprot = `AXI4_PROT_DATA;
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axi4.arqos = `AXI4_QOS_NORMAL;
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axi4.arregion = `AXI4_REGION_NORMAL;
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axi4.aruser = '0;
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axi4.arvalid = 1'b0;
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axi4.rready = 1'b0;
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cfg_apb4.psel = 1'b0;
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cfg_apb4.penable = 1'b0;
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cfg_apb4.pwrite = 1'b0;
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cfg_apb4.paddr = '0;
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cfg_apb4.pwdata = '0;
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cfg_apb4.pstrb = '0;
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end
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endtask
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task automatic apb_write(input logic [11:0] offset, input logic [31:0] data);
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begin
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@(negedge clk_i);
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cfg_apb4.psel = 1'b1;
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cfg_apb4.penable = 1'b0;
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cfg_apb4.pwrite = 1'b1;
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cfg_apb4.paddr = {20'd0, offset};
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cfg_apb4.pwdata = data;
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cfg_apb4.pstrb = 4'hF;
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@(posedge clk_i);
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@(negedge clk_i);
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cfg_apb4.penable = 1'b1;
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do @(posedge clk_i); while (!cfg_apb4.pready);
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if (cfg_apb4.pslverr) begin
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$fatal(1, "APB write SLVERR at %03x", offset);
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end
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@(negedge clk_i);
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cfg_apb4.psel = 1'b0;
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cfg_apb4.penable = 1'b0;
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cfg_apb4.pwrite = 1'b0;
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end
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endtask
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task automatic apb_read(input logic [11:0] offset);
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begin
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@(negedge clk_i);
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cfg_apb4.psel = 1'b1;
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cfg_apb4.penable = 1'b0;
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cfg_apb4.pwrite = 1'b0;
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cfg_apb4.paddr = {20'd0, offset};
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cfg_apb4.pstrb = 4'h0;
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@(posedge clk_i);
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@(negedge clk_i);
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cfg_apb4.penable = 1'b1;
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do @(posedge clk_i); while (!cfg_apb4.pready);
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if (cfg_apb4.pslverr) begin
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$fatal(1, "APB read SLVERR at %03x", offset);
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end
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s_apb_data = cfg_apb4.prdata;
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@(negedge clk_i);
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cfg_apb4.psel = 1'b0;
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cfg_apb4.penable = 1'b0;
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end
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endtask
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task automatic write_word(input logic [31:0] address, input logic [31:0] data,
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input logic [3:0] strobe);
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begin
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@(negedge clk_i);
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axi4.awaddr = address;
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axi4.awlen = 8'd0;
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axi4.awburst = `AXI4_BURST_TYPE_INCR;
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axi4.awlock = `AXI4_LOCK_NORM;
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axi4.awvalid = 1'b1;
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do @(posedge clk_i); while (!axi4.awready);
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@(negedge clk_i);
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axi4.awvalid = 1'b0;
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axi4.wdata = data;
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axi4.wstrb = strobe;
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axi4.wlast = 1'b1;
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axi4.wvalid = 1'b1;
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do @(posedge clk_i); while (!axi4.wready);
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@(negedge clk_i);
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axi4.wvalid = 1'b0;
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axi4.wlast = 1'b0;
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axi4.bready = 1'b1;
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do @(posedge clk_i); while (!axi4.bvalid);
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if (axi4.bresp != `AXI4_RESP_OKAY) begin
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$fatal(1, "AXI4 SDRAM write failed at %08x", address);
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end
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@(negedge clk_i);
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axi4.bready = 1'b0;
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end
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endtask
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task automatic read_word(input logic [31:0] address);
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begin
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@(negedge clk_i);
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axi4.araddr = address;
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axi4.arlen = 8'd0;
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axi4.arburst = `AXI4_BURST_TYPE_INCR;
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axi4.arlock = `AXI4_LOCK_NORM;
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axi4.arvalid = 1'b1;
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do @(posedge clk_i); while (!axi4.arready);
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@(negedge clk_i);
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axi4.arvalid = 1'b0;
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axi4.rready = 1'b1;
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do @(posedge clk_i); while (!axi4.rvalid);
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s_read_data = axi4.rdata;
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if (axi4.rresp != `AXI4_RESP_OKAY || !axi4.rlast) begin
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$fatal(1, "AXI4 SDRAM read failed at %08x", address);
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end
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@(negedge clk_i);
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axi4.rready = 1'b0;
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end
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endtask
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task automatic write_incr(input logic [31:0] address, input logic [7:0] length);
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integer beat;
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begin
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@(negedge clk_i);
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axi4.awaddr = address;
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axi4.awlen = length;
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axi4.awburst = `AXI4_BURST_TYPE_INCR;
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axi4.awvalid = 1'b1;
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do @(posedge clk_i); while (!axi4.awready);
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@(negedge clk_i);
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axi4.awvalid = 1'b0;
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for (beat = 0; beat <= length; beat++) begin
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axi4.wdata = 32'h1000_0000 + address + (beat * 4);
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axi4.wstrb = 4'hF;
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axi4.wlast = (beat == length);
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axi4.wvalid = 1'b1;
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do @(posedge clk_i); while (!axi4.wready);
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@(negedge clk_i);
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end
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axi4.wvalid = 1'b0;
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axi4.wlast = 1'b0;
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axi4.bready = 1'b1;
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do @(posedge clk_i); while (!axi4.bvalid);
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if (axi4.bresp != `AXI4_RESP_OKAY) begin
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$fatal(1, "AXI4 SDRAM INCR write failed at %08x", address);
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end
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@(negedge clk_i);
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axi4.bready = 1'b0;
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end
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endtask
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task automatic read_incr(input logic [31:0] address, input logic [7:0] length);
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integer beat;
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begin
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@(negedge clk_i);
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axi4.araddr = address;
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axi4.arlen = length;
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axi4.arburst = `AXI4_BURST_TYPE_INCR;
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axi4.arvalid = 1'b1;
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do @(posedge clk_i); while (!axi4.arready);
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@(negedge clk_i);
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axi4.arvalid = 1'b0;
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axi4.rready = 1'b1;
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for (beat = 0; beat <= length; beat++) begin
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do @(posedge clk_i); while (!axi4.rvalid);
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if (axi4.rdata !== (32'h1000_0000 + address + (beat * 4))) begin
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$fatal(1, "INCR read mismatch beat %0d got %08x", beat, axi4.rdata);
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end
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if (axi4.rresp != `AXI4_RESP_OKAY) begin
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$fatal(1, "INCR read SLVERR beat %0d", beat);
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end
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if (axi4.rlast !== (beat == length)) begin
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$fatal(1, "INCR RLAST mismatch beat %0d", beat);
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end
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@(negedge clk_i);
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end
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axi4.rready = 1'b0;
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end
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endtask
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initial begin
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#2_000_000;
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$fatal(1, "simulation timeout");
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end
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initial begin
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init_axi4();
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repeat (4) @(posedge clk_i);
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rst_n_i = 1'b1;
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$display("TB reset released");
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write_word(`SOC_ADDR_SDRAM_BASE + 32'h40, 32'h1357_9BDF, 4'b1111);
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read_word(`SOC_ADDR_SDRAM_BASE + 32'h40);
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if (s_read_data !== 32'h1357_9BDF) begin
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$fatal(1, "post-reset stalled SDRAM readback was %08x", s_read_data);
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end
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// Auto-init is already complete if the post-reset access returned OKAY.
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repeat (8000) @(posedge clk_i);
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$display("TB init wait done");
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apb_read(`APB4_SDRAM__STATUS);
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$display("TB STATUS=%08x", s_apb_data);
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if (!s_apb_data[`APB4_SDRAM__STATUS_READY]) begin
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$fatal(1, "SDRAM STATUS.READY was not set after auto-init");
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end
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apb_read(`APB4_SDRAM__IP_VERSION);
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if (s_apb_data !== `APB4_SDRAM__IP_VERSION_VALUE) begin
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$fatal(1, "SDRAM IP_VERSION mismatch %08x", s_apb_data);
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end
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apb_read(`APB4_SDRAM__CAPABILITY);
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if (s_apb_data !== `APB4_SDRAM__CAPABILITY_VALUE) begin
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$fatal(1, "SDRAM CAPABILITY mismatch %08x", s_apb_data);
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end
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write_word(`SOC_ADDR_SDRAM_BASE, 32'h1234_5678, 4'b1111);
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read_word(`SOC_ADDR_SDRAM_BASE);
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if (s_read_data !== 32'h1234_5678) begin
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$fatal(1, "full-word SDRAM readback was %08x", s_read_data);
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end
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write_word(`SOC_ADDR_SDRAM_BASE, 32'hA5A5_0000, 4'b1100);
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read_word(`SOC_ADDR_SDRAM_BASE);
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if (s_read_data !== 32'hA5A5_5678) begin
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$fatal(1, "masked SDRAM readback was %08x", s_read_data);
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end
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write_word(`SOC_ADDR_SDRAM_BASE + 32'h03FF_FFFC, 32'hCAFE_BABE, 4'b1111);
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read_word(`SOC_ADDR_SDRAM_BASE + 32'h03FF_FFFC);
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if (s_read_data !== 32'hCAFE_BABE) begin
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$fatal(1, "high-address SDRAM readback was %08x", s_read_data);
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end
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write_incr(`SOC_ADDR_SDRAM_BASE + 32'h100, 8'd3);
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read_incr(`SOC_ADDR_SDRAM_BASE + 32'h100, 8'd3);
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write_incr(`SOC_ADDR_SDRAM_BASE + 32'h200, 8'd7);
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read_incr(`SOC_ADDR_SDRAM_BASE + 32'h200, 8'd7);
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write_incr(`SOC_ADDR_SDRAM_BASE + 32'h300, 8'd15);
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read_incr(`SOC_ADDR_SDRAM_BASE + 32'h300, 8'd15);
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@(negedge clk_i);
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axi4.araddr = `SOC_ADDR_SDRAM_BASE;
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axi4.arlen = 8'd0;
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axi4.arlock = 1'b1;
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axi4.arvalid = 1'b1;
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do @(posedge clk_i); while (!axi4.arready);
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@(negedge clk_i);
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axi4.arvalid = 1'b0;
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axi4.arlock = `AXI4_LOCK_NORM;
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axi4.rready = 1'b1;
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do @(posedge clk_i); while (!axi4.rvalid);
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if (axi4.rresp != `AXI4_RESP_SLAVE_ERROR) begin
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$fatal(1, "exclusive read did not return SLVERR");
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end
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@(negedge clk_i);
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axi4.rready = 1'b0;
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apb_write(`APB4_SDRAM__COMMAND, 32'h1 << `APB4_SDRAM__COMMAND_PRECHARGE_ALL);
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read_word(`SOC_ADDR_SDRAM_BASE);
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if (s_read_data !== 32'hA5A5_5678) begin
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$fatal(1, "post-precharge SDRAM readback was %08x", s_read_data);
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end
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apb_write(`APB4_SDRAM__CTRL, 32'h1 << `APB4_SDRAM__CTRL_ENABLE);
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@(negedge clk_i);
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axi4.araddr = `SOC_ADDR_SDRAM_BASE;
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axi4.arlen = 8'd0;
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axi4.arburst = `AXI4_BURST_TYPE_INCR;
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axi4.arlock = `AXI4_LOCK_NORM;
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axi4.arvalid = 1'b1;
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do @(posedge clk_i); while (!axi4.arready);
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@(negedge clk_i);
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axi4.arvalid = 1'b0;
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axi4.rready = 1'b1;
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do @(posedge clk_i); while (!axi4.rvalid);
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if (axi4.rresp != `AXI4_RESP_SLAVE_ERROR) begin
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$fatal(1, "disabled-window read did not return SLVERR");
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end
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@(negedge clk_i);
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axi4.rready = 1'b0;
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$display("sdram data integrity test passed");
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$finish;
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end
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endmodule
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