mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-06 14:55:14 +00:00
maksyuki
075344df58
- Increased the number of masters in the AXI4 interconnect testbench from 5 to 6. - Added new testbench for SPI-SD clock functionality (spisd_clock_tb). - Introduced testbench for SPI-SD command engine (spisd_command_tb). - Created testbench for SPI-SD CRC calculation (spisd_crc_tb). - Implemented testbench for SPI-SD data handling (spisd_data_tb). - Developed wrapper testbench for SPI-SD with APB and training checks (spisd_wrapper_tb). - Added Python test suite for SPI-SD RTL regressions (test_spisd.py). - Created a test for verifying register parity between RTL and C header definitions (test_spisd_register_parity.py).
69 lines
2.0 KiB
Systemverilog
69 lines
2.0 KiB
Systemverilog
`timescale 1ns / 1ps
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module spisd_clock_tb;
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logic clk_i = 1'b0;
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logic rst_n_i = 1'b0;
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logic enable_i = 1'b0;
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logic pause_i = 1'b0;
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logic [15:0] half_period_i = 16'd2;
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logic sck_o;
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logic rise_tick_o;
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logic fall_tick_o;
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logic running_o;
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integer s_rise_count;
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integer s_fall_count;
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always #1 clk_i = ~clk_i;
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spisd_clock u_spisd_clock (
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.clk_i (clk_i),
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.rst_n_i (rst_n_i),
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.enable_i (enable_i),
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.pause_i (pause_i),
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.half_period_i(half_period_i),
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.sck_o (sck_o),
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.rise_tick_o (rise_tick_o),
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.fall_tick_o (fall_tick_o),
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.running_o (running_o)
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);
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always @(posedge clk_i) begin
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if (rise_tick_o) s_rise_count = s_rise_count + 1;
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if (fall_tick_o) s_fall_count = s_fall_count + 1;
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if (rise_tick_o && fall_tick_o) $fatal(1, "both SPI phases asserted");
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end
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initial begin
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s_rise_count = 0;
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s_fall_count = 0;
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repeat (2) @(posedge clk_i);
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rst_n_i = 1'b1;
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enable_i = 1'b1;
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repeat (16) @(posedge clk_i);
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if ((s_rise_count != 4) || (s_fall_count != 4) || !running_o) begin
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$fatal(1, "phase counts mismatch: rise=%0d fall=%0d", s_rise_count, s_fall_count);
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end
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wait (!sck_o);
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pause_i = 1'b1;
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repeat (8) @(posedge clk_i);
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if (sck_o || !running_o || (s_rise_count != 4) || (s_fall_count != 4)) begin
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$fatal(1, "low-phase pause failed");
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end
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pause_i = 1'b0;
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wait (sck_o);
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enable_i = 1'b0;
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repeat (6) @(posedge clk_i);
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if (sck_o || running_o || (s_rise_count != 5) || (s_fall_count != 5)) begin
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$fatal(1, "clock did not finish the active phase before stopping");
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end
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half_period_i = 16'd0;
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enable_i = 1'b1;
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repeat (4) @(posedge clk_i);
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if ((s_rise_count != 7) || (s_fall_count != 7)) begin
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$fatal(1, "zero divider did not map to one cycle");
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end
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$display("SPISD phase clock and low-only pause test passed");
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$finish;
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end
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endmodule
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