mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-06 14:55:14 +00:00
maksyuki
075344df58
- Increased the number of masters in the AXI4 interconnect testbench from 5 to 6. - Added new testbench for SPI-SD clock functionality (spisd_clock_tb). - Introduced testbench for SPI-SD command engine (spisd_command_tb). - Created testbench for SPI-SD CRC calculation (spisd_crc_tb). - Implemented testbench for SPI-SD data handling (spisd_data_tb). - Developed wrapper testbench for SPI-SD with APB and training checks (spisd_wrapper_tb). - Added Python test suite for SPI-SD RTL regressions (test_spisd.py). - Created a test for verifying register parity between RTL and C header definitions (test_spisd_register_parity.py).
30 lines
1.0 KiB
Systemverilog
30 lines
1.0 KiB
Systemverilog
`timescale 1ns / 1ps
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module spisd_crc_tb;
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logic [15:0] s_crc16;
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initial begin
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if (spisd_pkg::spisd_crc7_calc({2'b01, 6'd0, 32'd0}) != 7'h4A) begin
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$fatal(1, "CMD0 CRC7 vector failed");
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end
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if (spisd_pkg::spisd_crc7_calc({2'b01, 6'd8, 32'h0000_01AA}) != 7'h43) begin
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$fatal(1, "CMD8 CRC7 vector failed");
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end
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s_crc16 = 16'h0000;
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s_crc16 = spisd_pkg::spisd_crc16_byte(s_crc16, "1");
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s_crc16 = spisd_pkg::spisd_crc16_byte(s_crc16, "2");
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s_crc16 = spisd_pkg::spisd_crc16_byte(s_crc16, "3");
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s_crc16 = spisd_pkg::spisd_crc16_byte(s_crc16, "4");
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s_crc16 = spisd_pkg::spisd_crc16_byte(s_crc16, "5");
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s_crc16 = spisd_pkg::spisd_crc16_byte(s_crc16, "6");
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s_crc16 = spisd_pkg::spisd_crc16_byte(s_crc16, "7");
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s_crc16 = spisd_pkg::spisd_crc16_byte(s_crc16, "8");
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s_crc16 = spisd_pkg::spisd_crc16_byte(s_crc16, "9");
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if (s_crc16 != 16'h31C3) begin
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$fatal(1, "CRC16 vector failed: %h", s_crc16);
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end
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$display("SPISD CRC vectors passed");
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$finish;
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end
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endmodule
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