mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-06 14:55:14 +00:00
maksyuki
075344df58
- Increased the number of masters in the AXI4 interconnect testbench from 5 to 6. - Added new testbench for SPI-SD clock functionality (spisd_clock_tb). - Introduced testbench for SPI-SD command engine (spisd_command_tb). - Created testbench for SPI-SD CRC calculation (spisd_crc_tb). - Implemented testbench for SPI-SD data handling (spisd_data_tb). - Developed wrapper testbench for SPI-SD with APB and training checks (spisd_wrapper_tb). - Added Python test suite for SPI-SD RTL regressions (test_spisd.py). - Created a test for verifying register parity between RTL and C header definitions (test_spisd_register_parity.py).
221 lines
7.6 KiB
Systemverilog
221 lines
7.6 KiB
Systemverilog
`timescale 1ns / 1ps
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module spisd_data_tb;
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logic clk_i = 1'b0;
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logic rst_n_i = 1'b0;
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logic rise_tick_i = 1'b0;
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logic fall_tick_i = 1'b0;
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logic start_i = 1'b0;
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logic abort_i = 1'b0;
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spisd_pkg::spisd_data_direction_e direction_i = spisd_pkg::SpisdDataFromCard;
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logic multi_block_i = 1'b0;
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logic crc_check_i = 1'b1;
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logic [15:0] block_size_i = 16'd4;
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logic [15:0] block_count_i = 16'd1;
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logic [31:0] timeout_cycles_i = 32'd1000;
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logic [31:0] busy_timeout_cycles_i = 32'd1000;
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logic miso_i = 1'b1;
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logic mosi_o;
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logic clock_pause_o;
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logic tx_valid_i = 1'b0;
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logic tx_ready_o;
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logic [31:0] tx_data_i = 32'd0;
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logic [ 3:0] tx_strb_i = 4'd0;
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logic tx_last_i = 1'b0;
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logic rx_valid_o;
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logic rx_ready_i = 1'b0;
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logic [31:0] rx_data_o;
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logic [ 3:0] rx_strb_o;
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logic rx_last_o;
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logic busy_o;
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logic done_o;
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logic error_o;
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logic timeout_o;
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logic crc_error_o;
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logic busy_timeout_o;
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logic [ 7:0] error_code_o;
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logic [15:0] blocks_done_o;
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logic [87:0] s_write_serial;
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logic [15:0] s_write_crc;
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always #1 clk_i = ~clk_i;
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spisd_data u_spisd_data (
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.clk_i (clk_i),
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.rst_n_i (rst_n_i),
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.rise_tick_i (rise_tick_i),
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.fall_tick_i (fall_tick_i),
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.start_i (start_i),
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.abort_i (abort_i),
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.direction_i (direction_i),
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.multi_block_i (multi_block_i),
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.crc_check_i (crc_check_i),
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.block_size_i (block_size_i),
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.block_count_i (block_count_i),
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.timeout_cycles_i (timeout_cycles_i),
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.busy_timeout_cycles_i(busy_timeout_cycles_i),
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.miso_i (miso_i),
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.mosi_o (mosi_o),
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.clock_pause_o (clock_pause_o),
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.tx_valid_i (tx_valid_i),
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.tx_ready_o (tx_ready_o),
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.tx_data_i (tx_data_i),
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.tx_strb_i (tx_strb_i),
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.tx_last_i (tx_last_i),
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.rx_valid_o (rx_valid_o),
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.rx_ready_i (rx_ready_i),
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.rx_data_o (rx_data_o),
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.rx_strb_o (rx_strb_o),
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.rx_last_o (rx_last_o),
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.busy_o (busy_o),
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.done_o (done_o),
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.error_o (error_o),
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.timeout_o (timeout_o),
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.crc_error_o (crc_error_o),
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.busy_timeout_o (busy_timeout_o),
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.error_code_o (error_code_o),
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.blocks_done_o (blocks_done_o)
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);
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task automatic pulse_start;
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begin
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@(negedge clk_i);
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start_i = 1'b1;
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@(negedge clk_i);
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start_i = 1'b0;
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end
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endtask
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task automatic rise_bit(input logic value);
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begin
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@(negedge clk_i);
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miso_i = value;
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rise_tick_i = 1'b1;
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@(negedge clk_i);
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rise_tick_i = 1'b0;
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end
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endtask
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task automatic rise_byte(input logic [7:0] value);
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begin
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for (integer bit_index = 7; bit_index >= 0; bit_index--) begin
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rise_bit(value[bit_index]);
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end
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end
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endtask
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task automatic fall_capture;
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begin
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@(negedge clk_i);
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s_write_serial = {s_write_serial[86:0], mosi_o};
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fall_tick_i = 1'b1;
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@(negedge clk_i);
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fall_tick_i = 1'b0;
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end
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endtask
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task automatic consume_read_word;
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begin
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wait (rx_valid_o);
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if ((rx_data_o != 32'h4433_2211) || (rx_strb_o != 4'hF) || !rx_last_o || !clock_pause_o) begin
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$fatal(1, "read stream packing/backpressure failed: data=%h strb=%h last=%b pause=%b",
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rx_data_o, rx_strb_o, rx_last_o, clock_pause_o);
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end
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@(negedge clk_i);
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rx_ready_i = 1'b1;
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@(negedge clk_i);
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rx_ready_i = 1'b0;
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end
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endtask
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initial begin
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repeat (2) @(posedge clk_i);
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rst_n_i = 1'b1;
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direction_i = spisd_pkg::SpisdDataFromCard;
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pulse_start();
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rise_byte(8'hFF);
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rise_byte(8'hFE);
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rise_byte(8'h11);
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rise_byte(8'h22);
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rise_byte(8'h33);
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rise_byte(8'h44);
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consume_read_word();
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rise_byte(8'hDD);
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rise_byte(8'h33);
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wait (done_o);
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if (error_o || (blocks_done_o != 16'd1)) begin
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$fatal(1, "valid read block failed: err=%b code=%h blocks=%0d", error_o, error_code_o,
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blocks_done_o);
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end
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@(posedge clk_i);
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wait (!done_o);
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direction_i = spisd_pkg::SpisdDataFromCard;
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pulse_start();
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rise_byte(8'hFE);
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rise_byte(8'h11);
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rise_byte(8'h22);
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rise_byte(8'h33);
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rise_byte(8'h44);
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consume_read_word();
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rise_byte(8'h00);
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rise_byte(8'h00);
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wait (done_o);
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if (!error_o || !crc_error_o || (error_code_o != spisd_pkg::SpisdErrDataCrc)) begin
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$fatal(1, "read CRC fault was not classified");
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end
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@(posedge clk_i);
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wait (!done_o);
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direction_i = spisd_pkg::SpisdDataToCard;
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block_size_i = 16'd8;
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tx_data_i = 32'h4433_2211;
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tx_strb_i = 4'hF;
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tx_last_i = 1'b0;
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s_write_crc = 16'h0000;
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s_write_crc = spisd_pkg::spisd_crc16_byte(s_write_crc, 8'h11);
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s_write_crc = spisd_pkg::spisd_crc16_byte(s_write_crc, 8'h22);
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s_write_crc = spisd_pkg::spisd_crc16_byte(s_write_crc, 8'h33);
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s_write_crc = spisd_pkg::spisd_crc16_byte(s_write_crc, 8'h44);
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s_write_crc = spisd_pkg::spisd_crc16_byte(s_write_crc, 8'h55);
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s_write_crc = spisd_pkg::spisd_crc16_byte(s_write_crc, 8'h66);
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s_write_crc = spisd_pkg::spisd_crc16_byte(s_write_crc, 8'h77);
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s_write_crc = spisd_pkg::spisd_crc16_byte(s_write_crc, 8'h88);
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s_write_serial = '0;
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pulse_start();
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wait (tx_ready_o);
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@(negedge clk_i);
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tx_valid_i = 1'b1;
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@(negedge clk_i);
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tx_valid_i = 1'b0;
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repeat (40) fall_capture();
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wait (tx_ready_o);
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tx_data_i = 32'h8877_6655;
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tx_last_i = 1'b1;
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@(negedge clk_i);
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tx_valid_i = 1'b1;
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@(negedge clk_i);
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tx_valid_i = 1'b0;
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repeat (48) fall_capture();
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if (s_write_serial != {8'hFE, 64'h1122_3344_5566_7788, s_write_crc}) begin
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$fatal(1, "write token/payload/CRC serialization failed: got=%h crc=%h", s_write_serial,
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s_write_crc);
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end
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rise_bit(1'b0);
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rise_bit(1'b0);
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rise_bit(1'b1);
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rise_bit(1'b0);
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rise_bit(1'b1);
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rise_bit(1'b0);
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rise_bit(1'b1);
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wait (done_o);
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if (error_o || timeout_o || busy_timeout_o || (blocks_done_o != 16'd1)) begin
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$fatal(1, "write response/busy completion failed: err=%b code=%h blocks=%0d", error_o,
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error_code_o, blocks_done_o);
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end
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$display("SPISD read/write data, CRC, and backpressure test passed");
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$finish;
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end
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endmodule
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