mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-06 14:55:14 +00:00
maksyuki
2840d22e96
- Updated to integrate a coefficient engine and additional signals for coefficient handling. - Modified to include a coefficient engine, enhancing the encoding process with new signals. - Improved to validate generated blocks against expected values and added timeout handling. - Introduced for testing SRAM wrappers in JPEG workspace. - Enhanced test coverage in to reject invalid STA net drivers. - Updated to ensure proper coverage of canonical domains in timing contracts. - Added a new test for JPEG coefficient engine in . - Improved memory map tests in to validate public active MMIO regions. - Enhanced management core specification tests in to verify high-performance core specifications. - Added behavioral-only checks in to exclude synthesis and netlist consumers. - Updated SDRAM tests in to track active firmware memory. - Enhanced STA constraints tests in to cover current clock domains and net drivers.
91 lines
2.2 KiB
Systemverilog
91 lines
2.2 KiB
Systemverilog
`timescale 1ns / 1ps
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module tc_sram_jpeg_workspace_tb;
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logic clk = 1'b0;
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logic row_cs;
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logic [ 5:0] row_addr;
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logic [63:0] row_data_i;
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logic row_wren;
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logic [63:0] row_data_o;
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logic coeff_a_cs;
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logic [ 5:0] coeff_a_addr;
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logic [31:0] coeff_a_data_i;
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logic coeff_a_wren;
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logic [31:0] coeff_a_data_o;
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logic coeff_b_cs;
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logic [ 5:0] coeff_b_addr;
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logic [31:0] coeff_b_data_i;
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logic coeff_b_wren;
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logic [31:0] coeff_b_data_o;
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always #5 clk = ~clk;
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tc_sram_64x64 u_row_sram (
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.clk_i (clk),
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.cs_i (row_cs),
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.addr_i(row_addr),
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.data_i(row_data_i),
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.wren_i(row_wren),
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.data_o(row_data_o)
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);
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tc_sram_64x32_2p u_coeff_sram (
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.clk_i (clk),
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.a_cs_i (coeff_a_cs),
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.a_addr_i(coeff_a_addr),
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.a_data_i(coeff_a_data_i),
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.a_wren_i(coeff_a_wren),
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.a_data_o(coeff_a_data_o),
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.b_cs_i (coeff_b_cs),
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.b_addr_i(coeff_b_addr),
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.b_data_i(coeff_b_data_i),
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.b_wren_i(coeff_b_wren),
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.b_data_o(coeff_b_data_o)
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);
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initial begin
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row_cs = 1'b0;
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row_addr = '0;
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row_data_i = '0;
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row_wren = 1'b0;
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coeff_a_cs = 1'b0;
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coeff_a_addr = '0;
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coeff_a_data_i = '0;
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coeff_a_wren = 1'b0;
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coeff_b_cs = 1'b0;
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coeff_b_addr = '0;
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coeff_b_data_i = '0;
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coeff_b_wren = 1'b0;
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@(negedge clk);
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row_cs = 1'b1;
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row_wren = 1'b1;
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row_addr = 6'd47;
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row_data_i = 64'h0123_4567_89ab_cdef;
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coeff_a_cs = 1'b1;
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coeff_a_wren = 1'b1;
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coeff_a_addr = 6'd3;
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coeff_a_data_i = 32'h1122_3344;
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coeff_b_cs = 1'b1;
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coeff_b_wren = 1'b1;
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coeff_b_addr = 6'd61;
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coeff_b_data_i = 32'haabb_ccdd;
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@(negedge clk);
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row_wren = 1'b0;
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coeff_a_wren = 1'b0;
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coeff_b_wren = 1'b0;
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@(negedge clk);
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if (row_data_o !== 64'h0123_4567_89ab_cdef || coeff_a_data_o !== 32'h1122_3344 ||
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coeff_b_data_o !== 32'haabb_ccdd) begin
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$fatal(1, "JPEG SRAM wrapper data mismatch");
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end
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row_cs = 1'b0;
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coeff_a_cs = 1'b0;
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coeff_b_cs = 1'b0;
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$display("JPEG SRAM workspace wrapper test passed");
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$finish;
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end
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endmodule
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