mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-06 14:55:14 +00:00
maksyuki
e219973c45
- Introduced a new USB2 transaction engine testbench to validate the functionality of the USB2 transaction engine. - Updated clock and reset domain tests to include USB2 ULPI crossings. - Enhanced memory map tests to verify USB2 base addresses and performance offsets. - Modified pin map tests to ensure USB2 ULPI pins are correctly generated. - Updated SOC topology tests to account for USB2 peripherals and IRQ mappings. - Added static timing analysis constraints for USB2 clock domains. - Created dedicated USB2 tests for various components including packet RAM, descriptor validation, and transaction engine. - Implemented a register parity test to ensure ABI consistency between RTL and C header definitions.
217 lines
7.1 KiB
Systemverilog
217 lines
7.1 KiB
Systemverilog
`timescale 1ns / 1ps
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module usb2_dma_tb;
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logic clk_i = 1'b0;
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logic rst_n_i = 1'b0;
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logic start_i = 1'b0;
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logic abort_i = 1'b0;
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logic memory_to_packet_i = 1'b1;
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logic allow_short_i = 1'b0;
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logic [31:0] desc_base_i = 32'd0;
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logic [15:0] desc_limit_i = 16'd1;
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logic [31:0] transfer_bytes_i = 32'd5;
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logic packet_in_valid_i = 1'b0;
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logic packet_in_ready_o;
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logic [31:0] packet_in_data_i = '0;
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logic [ 3:0] packet_in_strb_i = '0;
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logic packet_in_last_i = 1'b0;
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logic packet_out_valid_o;
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logic packet_out_ready_i = 1'b1;
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logic [31:0] packet_out_data_o;
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logic [ 3:0] packet_out_strb_o;
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logic packet_out_last_o;
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logic busy_o;
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logic done_o;
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logic error_o;
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logic [ 7:0] error_code_o;
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logic [31:0] current_desc_o;
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logic [31:0] next_desc_o;
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logic [31:0] bytes_done_o;
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logic [31:0] frame_o;
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logic descriptor_irq_o;
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logic abort_done_o;
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integer output_count;
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logic [31:0] output_data [0:1];
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logic [ 3:0] output_strb [0:1];
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logic output_last [0:1];
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logic descriptor_irq_seen;
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axi4_if #(
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.ADDR_WIDTH(32),
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.DATA_WIDTH(32),
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.ID_WIDTH (1),
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.USER_WIDTH(1)
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) dma_axi4 (
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.aclk (clk_i),
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.aresetn(rst_n_i)
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);
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always #5 clk_i = ~clk_i;
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always_ff @(posedge clk_i) begin
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if (!rst_n_i) begin
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output_count <= 0;
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descriptor_irq_seen <= 1'b0;
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end else begin
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if (packet_out_valid_o && packet_out_ready_i) begin
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output_data[output_count] <= packet_out_data_o;
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output_strb[output_count] <= packet_out_strb_o;
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output_last[output_count] <= packet_out_last_o;
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output_count <= output_count + 1;
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end
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if (descriptor_irq_o) begin
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descriptor_irq_seen <= 1'b1;
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end
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end
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end
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usb2_dma #(
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.AddrWidth (32),
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.DataWidth (32),
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.MaxDescriptors(16)
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) u_usb2_dma (
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.clk_i (clk_i),
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.rst_n_i (rst_n_i),
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.start_i (start_i),
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.abort_i (abort_i),
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.memory_to_packet_i(memory_to_packet_i),
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.allow_short_i (allow_short_i),
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.desc_base_i (desc_base_i),
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.desc_limit_i (desc_limit_i),
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.transfer_bytes_i (transfer_bytes_i),
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.packet_in_valid_i (packet_in_valid_i),
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.packet_in_ready_o (packet_in_ready_o),
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.packet_in_data_i (packet_in_data_i),
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.packet_in_strb_i (packet_in_strb_i),
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.packet_in_last_i (packet_in_last_i),
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.packet_out_valid_o(packet_out_valid_o),
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.packet_out_ready_i(packet_out_ready_i),
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.packet_out_data_o (packet_out_data_o),
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.packet_out_strb_o (packet_out_strb_o),
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.packet_out_last_o (packet_out_last_o),
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.busy_o (busy_o),
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.done_o (done_o),
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.error_o (error_o),
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.error_code_o (error_code_o),
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.current_desc_o (current_desc_o),
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.next_desc_o (next_desc_o),
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.bytes_done_o (bytes_done_o),
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.frame_o (frame_o),
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.descriptor_irq_o (descriptor_irq_o),
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.abort_done_o (abort_done_o),
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.dma_axi4 (dma_axi4)
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);
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sdio_axi_memory_responder #(
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.DepthWords(16384)
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) u_memory (
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.clk_i (clk_i),
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.rst_n_i(rst_n_i),
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.axi4 (dma_axi4)
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);
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task automatic reset_dut;
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begin
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rst_n_i = 1'b0;
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repeat (4) @(posedge clk_i);
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rst_n_i = 1'b1;
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@(posedge clk_i);
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end
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endtask
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task automatic start_dma;
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begin
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@(negedge clk_i);
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start_i = 1'b1;
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@(negedge clk_i);
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start_i = 1'b0;
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end
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endtask
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task automatic send_packet_word(input logic [31:0] data_i, input logic [3:0] strb_i,
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input logic last_i);
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begin
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@(negedge clk_i);
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packet_in_data_i = data_i;
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packet_in_strb_i = strb_i;
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packet_in_last_i = last_i;
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packet_in_valid_i = 1'b1;
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while (!packet_in_ready_o) @(negedge clk_i);
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@(negedge clk_i);
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packet_in_valid_i = 1'b0;
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end
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endtask
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initial begin
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u_memory.clear_memory();
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reset_dut();
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// Memory-to-packet transfer splits at 4 KiB and finishes with one valid byte.
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u_memory.write_word(32'h0000_0000, 32'h0000_0FFC);
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u_memory.write_word(32'h0000_0004, 32'd5);
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u_memory.write_word(32'h0000_0008, 32'd0);
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u_memory.write_word(32'h0000_000C, 32'h0000_000D);
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u_memory.write_word(32'h0000_0010, 32'd0);
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u_memory.write_word(32'h0000_0014, 32'd0);
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u_memory.write_word(32'h0000_0018, 32'd0);
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u_memory.write_word(32'h0000_001C, 32'd0);
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u_memory.write_word(32'h0000_0FFC, 32'h4433_2211);
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u_memory.write_word(32'h0000_1000, 32'h0000_0055);
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memory_to_packet_i = 1'b1;
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start_dma();
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wait (done_o || error_o);
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@(posedge clk_i);
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if (error_o || (bytes_done_o != 32'd5) || (output_count != 2) ||
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(output_data[0] != 32'h4433_2211) || (output_strb[0] != 4'hF) || output_last[0] ||
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(output_data[1] != 32'h0000_0055) || (output_strb[1] != 4'h1) || !output_last[1] ||
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(u_memory.read_burst_count != 3) || (u_memory.max_read_beats > 16) ||
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(u_memory.read_word(
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32'h0000_0010
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) != 32'd5) || (u_memory.read_word(
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32'h0000_0014
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) != 32'h0001_0000) || (u_memory.read_word(
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32'h0000_000C
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) != 32'h0000_000C) || !descriptor_irq_seen) begin
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$fatal(1, "memory-to-packet DMA failed err=%b code=%h bytes=%0d outputs=%0d", error_o,
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error_code_o, bytes_done_o, output_count);
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end
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// Packet-to-memory transfer preserves tail strobes and commits OWN last.
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reset_dut();
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u_memory.write_word(32'h0000_0000, 32'h0000_0200);
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u_memory.write_word(32'h0000_0004, 32'd5);
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u_memory.write_word(32'h0000_0008, 32'd0);
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u_memory.write_word(32'h0000_000C, 32'h0000_000D);
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u_memory.write_word(32'h0000_0010, 32'd0);
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u_memory.write_word(32'h0000_0014, 32'd0);
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u_memory.write_word(32'h0000_0018, 32'd0);
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u_memory.write_word(32'h0000_001C, 32'd0);
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u_memory.write_word(32'h0000_0200, 32'd0);
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u_memory.write_word(32'h0000_0204, 32'd0);
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memory_to_packet_i = 1'b0;
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start_dma();
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send_packet_word(32'h8877_6655, 4'hF, 1'b0);
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send_packet_word(32'h0000_0099, 4'h1, 1'b1);
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wait (done_o || error_o);
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@(posedge clk_i);
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if (error_o || (bytes_done_o != 32'd5) || (u_memory.read_word(
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32'h0000_0200
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) != 32'h8877_6655) || (u_memory.read_word(
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32'h0000_0204
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) != 32'h0000_0099) || (u_memory.read_word(
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32'h0000_0010
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) != 32'd5) || (u_memory.read_word(
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32'h0000_0014
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) != 32'h0001_0000) || (u_memory.read_word(
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32'h0000_000C
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) != 32'h0000_000C) || !descriptor_irq_seen) begin
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$fatal(1, "packet-to-memory DMA failed err=%b code=%h bytes=%0d data=%h tail=%h", error_o,
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error_code_o, bytes_done_o, u_memory.read_word(32'h0000_0200), u_memory.read_word(
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32'h0000_0204));
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end
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$display("USB2 descriptor DMA test passed");
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$finish;
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end
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endmodule
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