mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-06 14:55:14 +00:00
maksyuki
e219973c45
- Introduced a new USB2 transaction engine testbench to validate the functionality of the USB2 transaction engine. - Updated clock and reset domain tests to include USB2 ULPI crossings. - Enhanced memory map tests to verify USB2 base addresses and performance offsets. - Modified pin map tests to ensure USB2 ULPI pins are correctly generated. - Updated SOC topology tests to account for USB2 peripherals and IRQ mappings. - Added static timing analysis constraints for USB2 clock domains. - Created dedicated USB2 tests for various components including packet RAM, descriptor validation, and transaction engine. - Implemented a register parity test to ensure ABI consistency between RTL and C header definitions.
214 lines
6.8 KiB
Systemverilog
214 lines
6.8 KiB
Systemverilog
`timescale 1ns / 1ps
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module usb2_packet_store_tb;
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logic clk_i = 1'b0;
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logic rst_n_i = 1'b0;
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logic fill_start_valid_i = 1'b0;
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logic fill_start_ready_o;
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logic [11:0] fill_base_i = '0;
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logic [14:0] fill_bytes_i = '0;
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logic fill_valid_i = 1'b0;
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logic fill_ready_o;
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logic [31:0] fill_data_i = '0;
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logic [ 3:0] fill_strb_i = '0;
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logic fill_last_i = 1'b0;
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logic fill_done_o;
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logic fill_error_o;
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logic drain_start_valid_i = 1'b0;
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logic drain_start_ready_o;
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logic [11:0] drain_base_i = '0;
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logic [14:0] drain_bytes_i = '0;
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logic drain_valid_o;
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logic drain_ready_i = 1'b1;
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logic [31:0] drain_data_o;
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logic [ 3:0] drain_strb_o;
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logic drain_last_o;
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logic drain_done_o;
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logic rx_start_valid_i = 1'b0;
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logic rx_start_ready_o;
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logic [11:0] rx_base_i = '0;
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logic [14:0] rx_limit_i = '0;
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logic rx_valid_i = 1'b0;
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logic rx_ready_o;
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logic [ 7:0] rx_data_i = '0;
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logic rx_commit_i = 1'b0;
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logic rx_cancel_i = 1'b0;
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logic rx_done_o;
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logic [14:0] rx_bytes_o;
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logic rx_overflow_o;
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logic tx_start_valid_i = 1'b0;
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logic tx_start_ready_o;
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logic [11:0] tx_base_i = '0;
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logic [14:0] tx_bytes_i = '0;
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logic tx_valid_o;
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logic tx_ready_i = 1'b1;
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logic [ 7:0] tx_data_o;
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logic tx_done_o;
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logic busy_o;
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logic ecc_corrected_o;
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logic ecc_uncorrectable_o;
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integer tx_count;
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integer drain_count;
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logic [ 7:0] tx_bytes [0:4];
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logic [31:0] drain_words [0:1];
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logic [ 3:0] drain_strb [0:1];
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always #5 clk_i = ~clk_i;
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always_ff @(posedge clk_i) begin
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if (!rst_n_i) begin
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tx_count <= 0;
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drain_count <= 0;
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end else begin
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if (tx_valid_o && tx_ready_i) begin
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tx_bytes[tx_count] <= tx_data_o;
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tx_count <= tx_count + 1;
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end
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if (drain_valid_o && drain_ready_i) begin
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drain_words[drain_count] <= drain_data_o;
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drain_strb[drain_count] <= drain_strb_o;
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drain_count <= drain_count + 1;
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end
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end
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end
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usb2_packet_store u_dut (
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.clk_i (clk_i),
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.rst_n_i (rst_n_i),
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.fill_start_valid_i (fill_start_valid_i),
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.fill_start_ready_o (fill_start_ready_o),
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.fill_base_i (fill_base_i),
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.fill_bytes_i (fill_bytes_i),
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.fill_valid_i (fill_valid_i),
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.fill_ready_o (fill_ready_o),
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.fill_data_i (fill_data_i),
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.fill_strb_i (fill_strb_i),
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.fill_last_i (fill_last_i),
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.fill_done_o (fill_done_o),
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.fill_error_o (fill_error_o),
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.drain_start_valid_i(drain_start_valid_i),
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.drain_start_ready_o(drain_start_ready_o),
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.drain_base_i (drain_base_i),
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.drain_bytes_i (drain_bytes_i),
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.drain_valid_o (drain_valid_o),
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.drain_ready_i (drain_ready_i),
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.drain_data_o (drain_data_o),
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.drain_strb_o (drain_strb_o),
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.drain_last_o (drain_last_o),
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.drain_done_o (drain_done_o),
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.rx_start_valid_i (rx_start_valid_i),
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.rx_start_ready_o (rx_start_ready_o),
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.rx_base_i (rx_base_i),
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.rx_limit_i (rx_limit_i),
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.rx_valid_i (rx_valid_i),
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.rx_ready_o (rx_ready_o),
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.rx_data_i (rx_data_i),
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.rx_commit_i (rx_commit_i),
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.rx_cancel_i (rx_cancel_i),
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.rx_done_o (rx_done_o),
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.rx_bytes_o (rx_bytes_o),
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.rx_overflow_o (rx_overflow_o),
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.tx_start_valid_i (tx_start_valid_i),
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.tx_start_ready_o (tx_start_ready_o),
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.tx_base_i (tx_base_i),
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.tx_bytes_i (tx_bytes_i),
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.tx_valid_o (tx_valid_o),
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.tx_ready_i (tx_ready_i),
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.tx_data_o (tx_data_o),
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.tx_done_o (tx_done_o),
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.busy_o (busy_o),
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.ecc_corrected_o (ecc_corrected_o),
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.ecc_uncorrectable_o(ecc_uncorrectable_o)
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);
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task automatic pulse_fill(input logic [31:0] data_i, input logic [3:0] strb_i,
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input logic last_i);
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begin
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@(negedge clk_i);
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fill_data_i = data_i;
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fill_strb_i = strb_i;
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fill_last_i = last_i;
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fill_valid_i = 1'b1;
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while (!fill_ready_o) @(negedge clk_i);
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@(negedge clk_i);
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fill_valid_i = 1'b0;
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end
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endtask
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task automatic pulse_rx(input logic [7:0] data_i);
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begin
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@(negedge clk_i);
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rx_data_i = data_i;
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rx_valid_i = 1'b1;
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while (!rx_ready_o) @(negedge clk_i);
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@(negedge clk_i);
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rx_valid_i = 1'b0;
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end
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endtask
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initial begin
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repeat (4) @(posedge clk_i);
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rst_n_i = 1'b1;
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@(negedge clk_i);
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fill_base_i = 12'd8;
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fill_bytes_i = 15'd5;
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fill_start_valid_i = 1'b1;
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@(negedge clk_i);
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fill_start_valid_i = 1'b0;
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pulse_fill(32'h4433_2211, 4'hF, 1'b0);
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pulse_fill(32'h0000_0055, 4'h1, 1'b1);
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wait (fill_done_o);
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if (fill_error_o) $fatal(1, "packet store fill failed");
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@(negedge clk_i);
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tx_base_i = 12'd8;
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tx_bytes_i = 15'd5;
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tx_start_valid_i = 1'b1;
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@(negedge clk_i);
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tx_start_valid_i = 1'b0;
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wait (tx_done_o);
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@(posedge clk_i);
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if ((tx_count != 5) || (tx_bytes[0] != 8'h11) || (tx_bytes[1] != 8'h22) ||
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(tx_bytes[2] != 8'h33) || (tx_bytes[3] != 8'h44) || (tx_bytes[4] != 8'h55)) begin
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$fatal(1, "packet store transmit mismatch count=%0d", tx_count);
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end
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@(negedge clk_i);
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rx_base_i = 12'd16;
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rx_limit_i = 15'd5;
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rx_start_valid_i = 1'b1;
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@(negedge clk_i);
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rx_start_valid_i = 1'b0;
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pulse_rx(8'hA1);
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pulse_rx(8'hB2);
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pulse_rx(8'hC3);
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pulse_rx(8'hD4);
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pulse_rx(8'hE5);
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@(negedge clk_i);
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rx_commit_i = 1'b1;
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@(negedge clk_i);
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rx_commit_i = 1'b0;
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wait (rx_done_o);
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if ((rx_bytes_o != 15'd5) || rx_overflow_o) $fatal(1, "packet store receive failed");
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@(negedge clk_i);
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drain_base_i = 12'd16;
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drain_bytes_i = 15'd5;
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drain_start_valid_i = 1'b1;
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@(negedge clk_i);
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drain_start_valid_i = 1'b0;
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wait (drain_done_o);
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@(posedge clk_i);
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if ((drain_count != 2) || (drain_words[0] != 32'hD4C3_B2A1) ||
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(drain_words[1][7:0] != 8'hE5) || (drain_strb[0] != 4'hF) ||
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(drain_strb[1] != 4'h1)) begin
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$fatal(1, "packet store drain mismatch count=%0d", drain_count);
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end
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if (ecc_corrected_o || ecc_uncorrectable_o) $fatal(1, "unexpected ECC event");
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$display("USB2 packet store paths passed");
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$finish;
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end
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endmodule
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