mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-06 14:55:14 +00:00
maksyuki
5d61b7e90a
- Updated RTL paths in various files to remove the 'ribp' prefix, reflecting the new directory structure. - Modified test descriptions to remove version indicators (e.g., V2, V3) for clarity and consistency. - Adjusted file references in scripts and tests to align with the new peripheral and multimedia directory structure. - Added a new test to ensure repository layout invariants, confirming the absence of deprecated paths.
247 lines
8.8 KiB
Systemverilog
247 lines
8.8 KiB
Systemverilog
`timescale 1ns / 1ps
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`include "ribp_uart_define.svh"
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module uart_tb;
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logic clk_i = 1'b0;
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logic rst_n_i = 1'b0;
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logic dma_tx_stall;
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logic dma_rx_stall;
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ribp_if ribp ();
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uart_if uart ();
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always #5 clk_i = ~clk_i;
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ribp_uart u_dut (
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.clk_i (clk_i),
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.rst_n_i (rst_n_i),
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.dma_tx_stall_o(dma_tx_stall),
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.dma_rx_stall_o(dma_rx_stall),
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.ribp (ribp),
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.uart (uart)
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);
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task automatic ribp_write(input logic [31:0] address, input logic [31:0] data,
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input logic [3:0] strobe, input logic expected_error);
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begin
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@(negedge clk_i);
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ribp.addr = address;
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ribp.wdata = data;
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ribp.wstrb = strobe;
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ribp.valid = 1'b1;
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while (!ribp.ready) begin
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@(posedge clk_i);
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#1;
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end
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if (ribp.resp_err !== expected_error) begin
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$fatal(1, "UART write %h error=%b expected=%b", address, ribp.resp_err, expected_error);
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end
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@(negedge clk_i);
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ribp.valid = 1'b0;
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ribp.wstrb = '0;
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end
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endtask
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task automatic ribp_read(input logic [31:0] address, input logic expected_error,
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output logic [31:0] data);
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begin
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@(negedge clk_i);
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ribp.addr = address;
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ribp.wdata = '0;
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ribp.wstrb = '0;
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ribp.valid = 1'b1;
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while (!ribp.ready) begin
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@(posedge clk_i);
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#1;
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end
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if (ribp.resp_err !== expected_error) begin
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$fatal(1, "UART read %h error=%b expected=%b", address, ribp.resp_err, expected_error);
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end
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data = ribp.rdata;
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@(negedge clk_i);
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ribp.valid = 1'b0;
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end
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endtask
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task automatic write_ok(input logic [31:0] address, input logic [31:0] data);
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begin
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ribp_write(address, data, 4'hF, 1'b0);
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end
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endtask
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task automatic configure_uart_flow(input logic [4:0] line_control, input logic [1:0] flow_control,
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input logic [6:0] rts_assert_level,
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input logic [6:0] rts_deassert_level,
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input logic [3:0] control);
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begin
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write_ok(`RIBP_UART_CTRL, 0);
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repeat (4) @(posedge clk_i);
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write_ok(`RIBP_UART_FIFO_CTRL, 3);
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write_ok(`RIBP_UART_BAUD_INT, 16);
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write_ok(`RIBP_UART_BAUD_FRAC, 0);
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write_ok(`RIBP_UART_LINE_CTRL, line_control);
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write_ok(`RIBP_UART_RTS_WATERMARK, {9'd0, rts_deassert_level, 9'd0, rts_assert_level});
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write_ok(`RIBP_UART_FLOW_CTRL, flow_control);
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write_ok(`RIBP_UART_CTRL, control);
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end
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endtask
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task automatic configure_uart(input logic [4:0] line_control, input logic [3:0] control);
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begin
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configure_uart_flow(line_control, 2'd0, 7'd32, 7'd48, control);
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end
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endtask
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task automatic send_external_8n1(input logic [7:0] data, input logic bad_stop);
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integer bit_index;
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begin
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uart.rx_i = 1'b0;
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repeat (16) @(posedge clk_i);
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for (bit_index = 0; bit_index < 8; bit_index = bit_index + 1) begin
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uart.rx_i = data[bit_index];
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repeat (16) @(posedge clk_i);
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end
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uart.rx_i = !bad_stop;
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repeat (16) @(posedge clk_i);
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uart.rx_i = 1'b1;
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repeat (24) @(posedge clk_i);
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end
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endtask
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initial begin
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logic [31:0] value;
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integer index;
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ribp.valid = 1'b0;
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ribp.addr = '0;
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ribp.wdata = '0;
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ribp.wstrb = '0;
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uart.rx_i = 1'b1;
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uart.cts_n_i = 1'b1;
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repeat (4) @(posedge clk_i);
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rst_n_i = 1'b1;
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repeat (4) @(posedge clk_i);
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if (uart.rts_n_o !== 1'b1) $fatal(1, "UART RTS_n was not released after reset");
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ribp_read(`RIBP_UART_IP_VERSION, 1'b0, value);
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if (value != 32'h0003_0000) $fatal(1, "UART IP version mismatch");
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ribp_read(`RIBP_UART_CAPABILITY, 1'b0, value);
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if (value != 32'h03FF_4040) $fatal(1, "UART capability mismatch");
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ribp_read(32'h0000_0002, 1'b1, value);
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ribp_read(`RIBP_UART_RXDATA, 1'b1, value);
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ribp_write(`RIBP_UART_RTS_WATERMARK, 32'h0002_0002, 4'hF, 1'b1);
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ribp_read(`RIBP_UART_ERROR_STATUS, 1'b0, value);
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if (!value[`UART_ERROR_CONFIG]) $fatal(1, "UART invalid RTS watermark was not reported");
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write_ok(`RIBP_UART_ERROR_STATUS, 7'h7F);
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configure_uart_flow(5'd3, 2'b01, 7'd32, 7'd48, 4'b0111);
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write_ok(`RIBP_UART_TXDATA, 8'hA5);
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repeat (220) @(posedge clk_i);
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ribp_read(`RIBP_UART_RXDATA, 1'b0, value);
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if (value[11:0] != 12'h0A5) $fatal(1, "UART 8N1 loopback mismatch: %h", value);
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configure_uart(5'd3, 4'b0001);
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write_ok(`RIBP_UART_TXDATA, 8'h5A);
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repeat (24) @(posedge clk_i);
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ribp_read(`RIBP_UART_STATUS, 1'b0, value);
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if (!value[`UART_STATUS_TX_BUSY]) $fatal(1, "UART TX did not start before disable");
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write_ok(`RIBP_UART_CTRL, 0);
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repeat (180) @(posedge clk_i);
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ribp_read(`RIBP_UART_STATUS, 1'b0, value);
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if (value[`UART_STATUS_TX_BUSY] || !value[`UART_STATUS_TX_EMPTY]) begin
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$fatal(1, "UART TX did not finish its active frame after disable: %h", value);
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end
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write_ok(`RIBP_UART_INTR_ENABLE, 7'h7F);
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write_ok(`RIBP_UART_INTR_TEST, 7'h20);
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ribp_read(`RIBP_UART_INTR_STATUS, 1'b0, value);
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if (!value[`UART_INTR_BREAK] || !uart.irq_o) $fatal(1, "UART interrupt test failed");
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write_ok(`RIBP_UART_INTR_STATE, 7'h7F);
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configure_uart_flow(5'd3, 2'b01, 7'd32, 7'd48, 4'b0001);
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write_ok(`RIBP_UART_INTR_ENABLE, 7'h40);
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write_ok(`RIBP_UART_TXDATA, 8'hC3);
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write_ok(`RIBP_UART_TXDATA, 8'h5C);
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repeat (32) @(posedge clk_i);
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ribp_read(`RIBP_UART_STATUS, 1'b0, value);
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if (!value[`UART_STATUS_TX_FLOW_BLOCKED] || value[`UART_STATUS_TX_BUSY] ||
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value[`UART_STATUS_CTS_ASSERTED]) begin
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$fatal(1, "UART CTS did not block a new frame: %h", value);
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end
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ribp_read(`RIBP_UART_FIFO_LEVEL, 1'b0, value);
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if (value[6:0] != 7'd2) $fatal(1, "UART CTS-blocked FIFO count mismatch: %h", value);
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uart.cts_n_i = 1'b0;
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repeat (32) @(posedge clk_i);
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ribp_read(`RIBP_UART_STATUS, 1'b0, value);
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if (!value[`UART_STATUS_CTS_ASSERTED] || !value[`UART_STATUS_TX_BUSY]) begin
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$fatal(1, "UART did not start after CTS assertion: %h", value);
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end
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uart.cts_n_i = 1'b1;
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repeat (200) @(posedge clk_i);
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ribp_read(`RIBP_UART_STATUS, 1'b0, value);
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if (!value[`UART_STATUS_TX_FLOW_BLOCKED] || value[`UART_STATUS_TX_BUSY]) begin
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$fatal(1, "UART CTS did not stop at the frame boundary: %h", value);
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end
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ribp_read(`RIBP_UART_FIFO_LEVEL, 1'b0, value);
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if (value[6:0] != 7'd1) $fatal(1, "UART frame-boundary FIFO count mismatch: %h", value);
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ribp_read(`RIBP_UART_INTR_STATUS, 1'b0, value);
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if (!value[`UART_INTR_CTS_CHANGE] || !uart.irq_o) begin
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$fatal(1, "UART CTS change interrupt failed: %h", value);
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end
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write_ok(`RIBP_UART_INTR_STATE, 7'h7F);
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uart.cts_n_i = 1'b0;
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repeat (220) @(posedge clk_i);
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ribp_read(`RIBP_UART_FIFO_LEVEL, 1'b0, value);
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if (value[6:0] != 7'd0) $fatal(1, "UART did not resume after CTS assertion: %h", value);
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configure_uart(5'd3, 4'b0010);
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fork
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send_external_8n1(8'h3C, 1'b1);
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join
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ribp_read(`RIBP_UART_RXDATA, 1'b0, value);
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if ((value[7:0] != 8'h3C) || !value[`UART_RXDATA_FRAME_ERROR]) begin
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$fatal(1, "UART frame error was not retained: %h", value);
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end
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configure_uart_flow(5'd3, 2'b10, 7'd1, 7'd2, 4'b0010);
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repeat (4) @(posedge clk_i);
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if (uart.rts_n_o !== 1'b0) $fatal(1, "UART RTS_n was not asserted for an empty RX FIFO");
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send_external_8n1(8'h12, 1'b0);
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if (uart.rts_n_o !== 1'b0) $fatal(1, "UART RTS_n asserted state did not hold below watermark");
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send_external_8n1(8'h34, 1'b0);
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if (uart.rts_n_o !== 1'b1) $fatal(1, "UART RTS_n was not released at high watermark");
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ribp_read(`RIBP_UART_RXDATA, 1'b0, value);
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repeat (2) @(posedge clk_i);
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if ((value[7:0] != 8'h12) || (uart.rts_n_o !== 1'b0)) begin
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$fatal(1, "UART RTS hysteresis did not reassert below low watermark: %h", value);
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end
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ribp_read(`RIBP_UART_RXDATA, 1'b0, value);
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if (value[7:0] != 8'h34) $fatal(1, "UART RTS test RX ordering mismatch: %h", value);
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write_ok(`RIBP_UART_CTRL, 0);
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repeat (4) @(posedge clk_i);
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write_ok(`RIBP_UART_FIFO_CTRL, 3);
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for (index = 0; index < 64; index = index + 1) begin
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write_ok(`RIBP_UART_TXDATA, index);
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end
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ribp_write(`RIBP_UART_TXDATA, 32'h55, 4'hF, 1'b1);
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ribp_read(`RIBP_UART_FIFO_LEVEL, 1'b0, value);
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if (value[6:0] != 7'd64) $fatal(1, "UART TX FIFO depth mismatch: %h", value);
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write_ok(`RIBP_UART_FIFO_CTRL, 3);
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write_ok(`RIBP_UART_DMA_CTRL, 3);
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if (!dma_tx_stall || !dma_rx_stall) $fatal(1, "Disabled UART asserted a DMA request");
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$display("UART register, FIFO, loopback, flow-control, interrupt, and DMA test passed");
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$finish;
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end
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initial begin
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repeat (20000) @(posedge clk_i);
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$fatal(1, "UART test timeout");
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end
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endmodule
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