mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-06 14:55:14 +00:00
maksyuki
de32aa2979
- Introduced a new testbench for the AXI4 interconnect () to validate fault classification for decode and access errors. - Updated and to reflect changes in bus naming conventions. - Enhanced to include AXI4-Stream interface checks and validate stream data transfers. - Modified to integrate AXI4-Stream interfaces for improved DMA testing. - Added new Python tests () to verify AXI4 to RIBP burst bridge functionality and interconnect fault classification. - Updated existing tests to include AXI4 interfaces and ensure proper error handling and response validation. - Adjusted memory map generation and test setups to accommodate new AXI4 interface requirements.
123 lines
4.2 KiB
Python
123 lines
4.2 KiB
Python
"""Directed tests for the SoC-owned RIB building blocks."""
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from __future__ import annotations
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import shutil
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import subprocess
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import sys
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from pathlib import Path
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ROOT = Path(__file__).resolve().parents[1]
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def test_bus_preserves_incr4_and_rejects_illegal_bursts(tmp_path: Path) -> None:
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iverilog = shutil.which("iverilog")
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vvp = shutil.which("vvp")
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if iverilog is None or vvp is None:
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return
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memory_map = tmp_path / "memory_map"
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subprocess.run(
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[
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sys.executable,
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str(ROOT / "rtl/mini/address_map/generate_memory_map.py"),
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"--map",
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str(ROOT / "rtl/mini/address_map/memory_map.json"),
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"--output-dir",
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str(memory_map),
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"--have-sram-if",
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"NO",
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],
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check=True,
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)
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source_list = tmp_path / "rib_bus.fl"
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source_list.write_text(
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"\n".join(
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[
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"+define+SV_ASSRT_DISABLE",
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f"+incdir+{memory_map / 'rtl'}",
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f"+incdir+{ROOT / 'rtl/mini/top'}",
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f"+incdir+{ROOT / 'rtl/managed/clusterip/common/rtl'}",
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str(ROOT / "rtl/managed/clusterip/common/rtl/interface/axi4_if.sv"),
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str(ROOT / "rtl/managed/clusterip/common/rtl/interface/ribp_if.sv"),
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str(ROOT / "rtl/managed/clusterip/common/rtl/interface/ram_if.sv"),
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str(ROOT / "rtl/mini/top/rib_if.sv"),
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str(ROOT / "rtl/managed/clusterip/common/rtl/utils/register.sv"),
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str(ROOT / "rtl/managed/clusterip/common/rtl/utils/spill_register.sv"),
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str(ROOT / "rtl/mini/top/ribp2rib.sv"),
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str(ROOT / "rtl/mini/top/rib2ribp.sv"),
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str(ROOT / "rtl/mini/top/rib_error_slave.sv"),
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str(ROOT / "rtl/mini/top/rib2ram.sv"),
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str(ROOT / "rtl/mini/top/bus.sv"),
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str(ROOT / "tests/rtl/rib_bus_tb.sv"),
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"",
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]
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),
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encoding="utf-8",
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)
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converted = tmp_path / "rib_bus_tb.v"
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subprocess.run(
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[
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sys.executable,
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str(ROOT / "rtl/mini/script/convt_sv2v.py"),
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"-f",
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str(source_list),
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"--output",
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str(converted),
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],
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check=True,
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)
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simulation = tmp_path / "rib_bus_tb"
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subprocess.run(
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[iverilog, "-g2012", "-s", "rib_bus_tb", "-o", str(simulation), str(converted)],
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check=True,
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)
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result = subprocess.run([vvp, str(simulation)], text=True, capture_output=True, check=True)
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assert "RIB burst arbitration and protocol test passed" in result.stdout
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def test_burst_sram_preserves_data_and_backpressure(tmp_path: Path) -> None:
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iverilog = shutil.which("iverilog")
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vvp = shutil.which("vvp")
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if iverilog is None or vvp is None:
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return
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source_list = tmp_path / "rib2ram.fl"
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source_list.write_text(
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"\n".join(
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[
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"+define+SV_ASSRT_DISABLE",
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f"+incdir+{ROOT / 'rtl/mini/top'}",
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f"+incdir+{ROOT / 'rtl/managed/clusterip/common/rtl'}",
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str(ROOT / "rtl/managed/clusterip/common/rtl/interface/ram_if.sv"),
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str(ROOT / "rtl/mini/top/rib_if.sv"),
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str(ROOT / "rtl/managed/clusterip/common/rtl/utils/register.sv"),
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str(ROOT / "rtl/managed/clusterip/common/rtl/utils/spill_register.sv"),
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str(ROOT / "rtl/mini/top/rib2ram.sv"),
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str(ROOT / "tests/rtl/rib2ram_tb.sv"),
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"",
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]
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),
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encoding="utf-8",
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)
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converted = tmp_path / "rib2ram_tb.v"
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subprocess.run(
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[
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sys.executable,
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str(ROOT / "rtl/mini/script/convt_sv2v.py"),
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"-f",
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str(source_list),
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"--output",
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str(converted),
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],
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check=True,
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)
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simulation = tmp_path / "rib2ram_tb"
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subprocess.run(
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[iverilog, "-g2012", "-s", "rib2ram_tb", "-o", str(simulation), str(converted)],
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check=True,
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)
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result = subprocess.run([vvp, str(simulation)], text=True, capture_output=True, check=True)
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assert "RIB SRAM pipeline test passed" in result.stdout
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