mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-04 22:32:36 +00:00
maksyuki
62d112c4e6
- Introduced to validate AXI4 interface for 64-bit on-chip SRAM. - Added to test resource controller functionality including ownership, IRQ handling, and cache handshake. - Updated to include resource controller interface. - Enhanced to cover additional IRQ scenarios. - Added new tests in for AXI4 target guard timeout and isolation. - Updated to reflect changes in the high-performance profile. - Modified to verify on-chip SRAM bank configurations. - Added for directed verification of resource controller. - Updated to check SDRAM mapped window coverage. - Enhanced to ensure correct IRQ mappings and APB target generation.
222 lines
8.8 KiB
C
222 lines
8.8 KiB
C
#include <stddef.h>
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#include <stdint.h>
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#include <retrosoc/core/soc.h>
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#include <retrosoc/hal/extension.h>
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#include <retrosoc/hal/resource.h>
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#define RS_EXTENSION_IDENTIFICATION_OFFSET UINT32_C(0x000)
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#define RS_EXTENSION_VERSION_OFFSET UINT32_C(0x004)
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#define RS_EXTENSION_CAPABILITY_OFFSET UINT32_C(0x008)
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#define RS_EXTENSION_OWNER_OFFSET UINT32_C(0x00C)
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#define RS_EXTENSION_COMMAND_OFFSET UINT32_C(0x010)
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#define RS_EXTENSION_STATUS_OFFSET UINT32_C(0x014)
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#define RS_EXTENSION_READ_BASE_OFFSET UINT32_C(0x018)
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#define RS_EXTENSION_READ_LIMIT_OFFSET UINT32_C(0x01C)
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#define RS_EXTENSION_WRITE_BASE_OFFSET UINT32_C(0x020)
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#define RS_EXTENSION_WRITE_LIMIT_OFFSET UINT32_C(0x024)
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#define RS_EXTENSION_TIMEOUT_OFFSET UINT32_C(0x028)
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#define RS_EXTENSION_DMA_SOURCE_OFFSET UINT32_C(0x100)
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#define RS_EXTENSION_DMA_DESTINATION_OFFSET UINT32_C(0x104)
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#define RS_EXTENSION_DMA_LENGTH_OFFSET UINT32_C(0x108)
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#define RS_EXTENSION_DMA_COMMAND_OFFSET UINT32_C(0x10C)
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#define RS_EXTENSION_DMA_STATUS_OFFSET UINT32_C(0x110)
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#define RS_EXTENSION_REGISTER_SIZE UINT32_C(4)
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#define RS_EXTENSION_OWNER_LOCK UINT32_C(0x00000100)
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#define RS_EXTENSION_COMMAND_QUIESCE UINT32_C(0x00000001)
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#define RS_EXTENSION_COMMAND_RESET UINT32_C(0x00000002)
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#define RS_EXTENSION_COMMAND_CLEAR_FAULT UINT32_C(0x00000004)
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#define RS_EXTENSION_DMA_START UINT32_C(0x00000001)
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#define RS_EXTENSION_DMA_ABORT UINT32_C(0x00000002)
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#define RS_EXTENSION_DMA_STATUS_BUSY UINT32_C(0x00000001)
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#define RS_EXTENSION_DMA_STATUS_DONE UINT32_C(0x00000002)
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#define RS_EXTENSION_DMA_STATUS_FAULT UINT32_C(0x00000004)
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static bool rs_extension_slot_valid(rs_extension_slot_t slot) {
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return (slot == RS_EXTENSION_SLOT_L) || (slot == RS_EXTENSION_SLOT_H);
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}
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static bool rs_extension_offset_valid(uint32_t offset) {
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return ((offset & (RS_EXTENSION_REGISTER_SIZE - UINT32_C(1))) == 0U) &&
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(offset <= (RS_SOC_APB4_EXT_L_SIZE - RS_EXTENSION_REGISTER_SIZE));
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}
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static uintptr_t rs_extension_base(rs_extension_slot_t slot) {
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return (slot == RS_EXTENSION_SLOT_L) ? (uintptr_t)RS_SOC_APB4_EXT_L_BASE
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: (uintptr_t)RS_SOC_APB4_EXT_H_BASE;
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}
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static volatile uint32_t *rs_extension_register(rs_extension_slot_t slot, uint32_t offset) {
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return (volatile uint32_t *)(rs_extension_base(slot) + (uintptr_t)offset);
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}
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static rs_status_t rs_extension_write(rs_extension_slot_t slot, uint32_t offset, uint32_t value) {
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if (!rs_extension_slot_valid(slot) || !rs_extension_offset_valid(offset)) {
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return RS_EINVAL;
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}
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*rs_extension_register(slot, offset) = value;
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return RS_OK;
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}
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rs_status_t rs_extension_read(rs_extension_slot_t slot, uint32_t offset, uint32_t *value) {
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if ((value == NULL) || !rs_extension_slot_valid(slot) || !rs_extension_offset_valid(offset)) {
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return RS_EINVAL;
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}
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*value = *rs_extension_register(slot, offset);
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return RS_OK;
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}
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rs_status_t rs_extension_probe(rs_extension_slot_t slot,
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rs_extension_capabilities_t *capabilities) {
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uint32_t capability;
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if (capabilities == NULL) {
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return RS_EINVAL;
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}
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if ((rs_extension_read(slot, RS_EXTENSION_IDENTIFICATION_OFFSET,
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&capabilities->identification) != RS_OK) ||
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(rs_extension_read(slot, RS_EXTENSION_VERSION_OFFSET, &capabilities->version) != RS_OK) ||
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(rs_extension_read(slot, RS_EXTENSION_CAPABILITY_OFFSET, &capability) != RS_OK)) {
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return RS_EINVAL;
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}
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capabilities->interrupt_count = (uint8_t)((capability >> 8U) & UINT32_C(0xFF));
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capabilities->data_master = (capability & UINT32_C(0x2)) != 0U;
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capabilities->stream = (capability & UINT32_C(0x4)) != 0U;
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capabilities->local_sram = (capability & UINT32_C(0x8)) != 0U;
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return RS_OK;
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}
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rs_status_t rs_extension_get_status(rs_extension_slot_t slot, rs_extension_status_t *status) {
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uint32_t owner;
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uint32_t lifecycle;
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if (status == NULL) {
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return RS_EINVAL;
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}
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if ((rs_extension_read(slot, RS_EXTENSION_OWNER_OFFSET, &owner) != RS_OK) ||
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(rs_extension_read(slot, RS_EXTENSION_STATUS_OFFSET, &lifecycle) != RS_OK)) {
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return RS_EINVAL;
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}
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status->owner = (rs_extension_owner_t)(owner & UINT32_C(0x3));
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status->owner_locked = (owner & RS_EXTENSION_OWNER_LOCK) != 0U;
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status->present = (lifecycle & UINT32_C(0x1)) != 0U;
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status->idle = (lifecycle & UINT32_C(0x2)) != 0U;
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status->quiesced = (lifecycle & UINT32_C(0x4)) != 0U;
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status->in_reset = (lifecycle & UINT32_C(0x8)) != 0U;
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status->fault = (lifecycle & UINT32_C(0x10)) != 0U;
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return RS_OK;
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}
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rs_status_t rs_extension_set_owner(rs_extension_slot_t slot, rs_extension_owner_t owner,
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bool lock) {
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uint32_t value;
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rs_status_t status;
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if ((owner != RS_EXTENSION_OWNER_LP) && (owner != RS_EXTENSION_OWNER_HP)) {
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return RS_EINVAL;
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}
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value = (uint32_t)owner;
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if (lock) {
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value |= RS_EXTENSION_OWNER_LOCK;
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}
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if (slot == RS_EXTENSION_SLOT_H) {
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status = rs_resource_set_owner(RS_RESOURCE_EXT_H, (rs_resource_owner_t)owner, lock);
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if (status != RS_OK) {
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return status;
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}
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}
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return rs_extension_write(slot, RS_EXTENSION_OWNER_OFFSET, value);
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}
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rs_status_t rs_extension_set_lifecycle(rs_extension_slot_t slot, bool quiesce, bool reset,
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bool clear_fault) {
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uint32_t command = 0U;
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rs_status_t status;
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if (quiesce) {
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command |= RS_EXTENSION_COMMAND_QUIESCE;
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}
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if (reset) {
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command |= RS_EXTENSION_COMMAND_RESET;
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}
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if (clear_fault) {
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command |= RS_EXTENSION_COMMAND_CLEAR_FAULT;
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}
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if (slot == RS_EXTENSION_SLOT_H) {
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status = rs_resource_set_lifecycle(RS_RESOURCE_EXT_H, quiesce, reset);
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if (status != RS_OK) {
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return status;
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}
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if (clear_fault && (rs_resource_clear_fault(RS_RESOURCE_EXT_H) != RS_OK)) {
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return RS_EIO;
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}
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}
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return rs_extension_write(slot, RS_EXTENSION_COMMAND_OFFSET, command);
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}
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rs_status_t rs_extension_configure_acl(rs_extension_slot_t slot,
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const rs_extension_acl_t *configuration) {
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if ((configuration == NULL) || !rs_extension_slot_valid(slot) ||
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(configuration->read_limit < configuration->read_base) ||
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(configuration->write_limit < configuration->write_base) ||
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(configuration->timeout_cycles == 0U)) {
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return RS_EINVAL;
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}
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if (slot != RS_EXTENSION_SLOT_H) {
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return RS_ENOTSUP;
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}
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if ((rs_extension_write(slot, RS_EXTENSION_READ_BASE_OFFSET, configuration->read_base) !=
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RS_OK) ||
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(rs_extension_write(slot, RS_EXTENSION_READ_LIMIT_OFFSET, configuration->read_limit) !=
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RS_OK) ||
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(rs_extension_write(slot, RS_EXTENSION_WRITE_BASE_OFFSET, configuration->write_base) !=
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RS_OK) ||
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(rs_extension_write(slot, RS_EXTENSION_WRITE_LIMIT_OFFSET, configuration->write_limit) !=
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RS_OK) ||
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(rs_extension_write(slot, RS_EXTENSION_TIMEOUT_OFFSET, configuration->timeout_cycles) !=
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RS_OK)) {
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return RS_EINVAL;
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}
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return RS_OK;
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}
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rs_status_t rs_extension_dma_start(uintptr_t source, uintptr_t destination, uint32_t byte_count) {
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if (((source | destination) & (uintptr_t)UINT32_C(0x7)) != (uintptr_t)0U ||
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(byte_count == 0U) || (source > (uintptr_t)UINT32_MAX) ||
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(destination > (uintptr_t)UINT32_MAX)) {
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return RS_EINVAL;
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}
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if ((rs_extension_write(RS_EXTENSION_SLOT_H, RS_EXTENSION_DMA_SOURCE_OFFSET,
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(uint32_t)source) != RS_OK) ||
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(rs_extension_write(RS_EXTENSION_SLOT_H, RS_EXTENSION_DMA_DESTINATION_OFFSET,
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(uint32_t)destination) != RS_OK) ||
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(rs_extension_write(RS_EXTENSION_SLOT_H, RS_EXTENSION_DMA_LENGTH_OFFSET, byte_count) !=
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RS_OK) ||
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(rs_extension_write(RS_EXTENSION_SLOT_H, RS_EXTENSION_DMA_COMMAND_OFFSET,
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RS_EXTENSION_DMA_START) != RS_OK)) {
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return RS_EIO;
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}
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return RS_OK;
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}
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rs_status_t rs_extension_dma_abort(void) {
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return rs_extension_write(RS_EXTENSION_SLOT_H, RS_EXTENSION_DMA_COMMAND_OFFSET,
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RS_EXTENSION_DMA_ABORT);
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}
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rs_status_t rs_extension_dma_get_status(rs_extension_dma_status_t *status) {
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uint32_t value;
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if (status == NULL) {
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return RS_EINVAL;
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}
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if (rs_extension_read(RS_EXTENSION_SLOT_H, RS_EXTENSION_DMA_STATUS_OFFSET, &value) != RS_OK) {
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return RS_EIO;
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}
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status->busy = (value & RS_EXTENSION_DMA_STATUS_BUSY) != 0U;
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status->done = (value & RS_EXTENSION_DMA_STATUS_DONE) != 0U;
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status->fault = (value & RS_EXTENSION_DMA_STATUS_FAULT) != 0U;
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return RS_OK;
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}
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