mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-05 06:32:37 +00:00
maksyuki
c8187284d0
- Introduced to create pad-aware timing constraints for the Tiny IHP130 chip flow. - Added to create a checksummed delivery archive for the Tiny LibreLane implementation. - Created for synthesis-only header of the locked IHP SRAM macro physical views. - Implemented to limit OpenSTA report enumeration for path counts. - Updated to include power pad definitions. - Enhanced to handle power pad counts and validation. - Added tests for Tiny flow and pin map validation, including power pad overrides and constraints.
176 lines
7.3 KiB
Python
176 lines
7.3 KiB
Python
"""Tests for the Tiny IHP130 LibreLane chip flow."""
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from __future__ import annotations
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import importlib.util
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import re
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from pathlib import Path
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from types import SimpleNamespace
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ROOT = Path(__file__).resolve().parents[1]
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PIN_MAP = ROOT / "rtl/tiny/pin_map/pin_map.json"
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DOMAINS = ROOT / "rtl/tiny/integration/clock_reset_domains.json"
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FLOW_ROOT = ROOT / "physical/librelane/tiny"
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BONDPAD_LEF = ROOT / "physical/librelane/bondpad/bondpad_70x70.lef"
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def load_module(name: str, path: Path):
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spec = importlib.util.spec_from_file_location(name, path)
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assert spec is not None and spec.loader is not None
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module = importlib.util.module_from_spec(spec)
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spec.loader.exec_module(module)
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return module
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def chip_arguments(tmp_path: Path) -> SimpleNamespace:
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return SimpleNamespace(
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pin_map=PIN_MAP,
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rtl=tmp_path / "retrosoc_tiny_asic_sources.sv",
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sdc=tmp_path / "retrosoc_tiny_chip.sdc",
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pdn=FLOW_ROOT / "pdn_cfg.tcl",
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bondpad_gds=tmp_path / "bondpad_70x70.gds",
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bondpad_lef=BONDPAD_LEF,
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sram_vh=FLOW_ROOT / "sram_blackboxes.vh",
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ext_clk_hz=24_000_000,
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have_sram_macro=True,
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sram_size_kib=128,
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output=tmp_path / "config.json",
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)
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def test_chip_config_places_every_signal_and_power_pad_once(tmp_path: Path) -> None:
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module = load_module(
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"retrosoc_tiny_librelane_config", FLOW_ROOT / "scripts/generate_chip_config.py"
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)
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config = module.build_config(chip_arguments(tmp_path))
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sides = {name: config[f"PAD_{name.upper()}"] for name in module.SIDE_ORDER}
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placed = [instance for side in module.SIDE_ORDER for instance in sides[side]]
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assert len(placed) == 84
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assert len(placed) == len(set(placed))
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assert {side: len(instances) for side, instances in sides.items()} == {
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"south": 19,
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"east": 24,
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"north": 17,
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"west": 24,
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}
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assert sum(item.startswith("vdd_pads[") for item in placed) == 8
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assert sum(item.startswith("vss_pads[") for item in placed) == 8
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assert sum(item.startswith("iovdd_pads[") for item in placed) == 8
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assert sum(item.startswith("iovss_pads[") for item in placed) == 8
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assert "u_extclk_i_pad.u_sg13g2_IOPadIn" in sides["south"]
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assert "u_jtag_tck_i_pad.u_sg13g2_IOPadIn" in sides["south"]
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assert "u_uart0_tx_o_pad.u_sg13g2_IOPadOut4mA" in sides["south"]
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assert "u_xpi_sck_o_pad.u_sg13g2_IOPadOut4mA" in sides["north"]
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assert "u_gpio_0_io_pad.u_sg13g2_IOPadInOut4mA" in sides["east"]
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assert "u_gpio_15_io_pad.u_sg13g2_IOPadInOut4mA" in sides["east"]
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assert "u_gpio_16_io_pad.u_sg13g2_IOPadInOut4mA" in sides["west"]
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assert "u_gpio_31_io_pad.u_sg13g2_IOPadInOut4mA" in sides["west"]
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assert config["meta"] == {"version": 3, "flow": "Chip"}
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assert config["DESIGN_NAME"] == "retrosoc_tiny_asic"
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assert config["DIE_AREA"] == [0, 0, 4700, 4700]
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assert config["CORE_AREA"] == [365, 365, 4335, 4335]
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assert config["CLOCK_PORT"] == ["extclk_i_pad", "jtag_tck_i_pad"]
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assert config["CLOCK_PERIOD"] == 1_000_000_000 / 24_000_000
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assert config["PL_TARGET_DENSITY_PCT"] == 45
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assert config["USE_SLANG"] is True
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assert config["SLANG_ARGUMENTS"] == ["--keep-hierarchy"]
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assert config["SYNTH_HIERARCHY_MODE"] == "deferred_flatten"
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assert config["SYNTH_KEEP_HIERARCHY_MODULES"] == [
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"sg13g2_IOPadVdd",
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"sg13g2_IOPadVss",
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"sg13g2_IOPadIOVdd",
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"sg13g2_IOPadIOVss",
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]
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assert config["RUN_CTS"] is False
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assert config["ERROR_ON_SYNTH_CHECKS"] is False
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assert config["EXTRA_EXCLUDED_CELLS"] == ["sg13g2_IOPad*"]
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assert config["VDD_NETS"] == ["VDD"]
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assert config["GND_NETS"] == ["VSS"]
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assert config["PAD_CFG"].endswith("physical/librelane/tiny/pad_cfg.tcl")
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assert config["PDN_ENABLE_PINS"] is True
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assert config["ERROR_ON_PDN_VIOLATIONS"] is True
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assert config["STA_EXTRA_CORNER_TCL_FILE"].endswith(
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"physical/librelane/tiny/sta_report_limit.tcl"
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)
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assert config["PAD_BONDPAD_NAME"] == "bondpad_70x70"
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assert set(config["MACROS"]) == {"RM_IHPSG13_1P_1024x32_c2_bm_bist"}
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def test_chip_config_covers_every_onchip_sram_bank(tmp_path: Path) -> None:
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module = load_module(
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"retrosoc_tiny_librelane_sram_config", FLOW_ROOT / "scripts/generate_chip_config.py"
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)
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config = module.build_config(chip_arguments(tmp_path))
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macro = config["MACROS"]["RM_IHPSG13_1P_1024x32_c2_bm_bist"]
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assert len(macro["instances"]) == 32
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assert (
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"u_soc.u_sram.gen_memory.gen_bank[0].u_ram.u_mem" in macro["instances"]
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)
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assert (
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"u_soc.u_sram.gen_memory.gen_bank[31].u_ram.u_mem" in macro["instances"]
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)
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for instance in macro["instances"].values():
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x, y = instance["location"]
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assert 365 <= x <= 4335
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assert 365 <= y <= 4335
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assert instance["orientation"] == "N"
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assert len(config["PDN_MACRO_CONNECTIONS"]) == 64
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assert any(
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"gen_bank.*0.*\\.u_ram" in connection
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for connection in config["PDN_MACRO_CONNECTIONS"]
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)
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blackboxes = (FLOW_ROOT / "sram_blackboxes.vh").read_text(encoding="utf-8")
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assert "module RM_IHPSG13_1P_1024x32_c2_bm_bist" in blackboxes
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assert "RM_IHPSG13_1P_4096x16_c3_bm_bist" not in blackboxes
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def test_chip_sdc_is_pad_aware_and_does_not_false_path_all_io() -> None:
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module = load_module(
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"retrosoc_tiny_librelane_sdc", FLOW_ROOT / "scripts/generate_sdc.py"
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)
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arguments = SimpleNamespace(
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domains=DOMAINS,
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pin_map=PIN_MAP,
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ext_clk_hz=24_000_000,
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)
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sdc = module.render(arguments)
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assert "u_extclk_i_pad.u_sg13g2_IOPadIn/p2c" in sdc
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assert "u_jtag_tck_i_pad.u_sg13g2_IOPadIn/p2c" in sdc
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assert "u_clock_buffer.u_sg13g2_buf_1/X" in sdc
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assert "create_clock -name clk_external -period 41.6666666667" in sdc
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assert "create_clock -name clk_jtag -period 100" in sdc
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assert "create_generated_clock -name clk_system" in sdc
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assert "set_clock_groups -name retrosoc_async -asynchronous" in sdc
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assert "-group [get_clocks {clk_external clk_system}]" in sdc
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assert "-group [get_clocks {clk_jtag}]" in sdc
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assert "set_input_delay -max" in sdc
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assert "set_output_delay -max" in sdc
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assert "set_false_path -from $reset_ext_rst_n_i_pad" in sdc
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assert "set_false_path -from $reset_jtag_trst_n_i_pad" in sdc
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assert "set_false_path -from [all_inputs]" not in sdc
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assert "set_false_path -to [all_outputs]" not in sdc
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def test_tiny_flow_exposes_chip_target_only() -> None:
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makefile = (FLOW_ROOT / "Makefile").read_text(encoding="utf-8")
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top_makefile = (ROOT / "Makefile").read_text(encoding="utf-8")
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assert "librelane-chip:" in makefile
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assert "librelane-core:" not in makefile
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assert "--soc TINY" in makefile
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assert "--source-filelist-dir" in makefile
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assert re.search(r"ifeq \(\$\(SOC\),TINY\)\ninclude physical/librelane/tiny/Makefile", top_makefile)
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assert "include physical/librelane/mini/Makefile" in top_makefile
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doctor = (FLOW_ROOT / "scripts/doctor.py").read_text(encoding="utf-8")
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assert "EXPECTED_SIGNAL_PADS = 52" in doctor
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pad_cfg = (FLOW_ROOT / "pad_cfg.tcl").read_text(encoding="utf-8")
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assert "vdd sg13g2_IOPadVdd 8" in pad_cfg
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assert "iovss sg13g2_IOPadIOVss 8" in pad_cfg
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pdn = (FLOW_ROOT / "pdn_cfg.tcl").read_text(encoding="utf-8")
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assert "RM_IHPSG13_1P_1024x32_c2_bm_bist" in pdn
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assert "RM_IHPSG13_1P_4096x16_c3_bm_bist" not in pdn
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