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maksyuki
65c19e7005
Complete the integration manual chapter 3 cell swap (the ICG half; the SRAM half landed earlier). Three new reviewed overrides, registered in generate_openc906.py with sha256 pins on the vendored files and added to the generated-filelist stamp prerequisites: - gated_clk_cell.v (216 CPU instances) and tdt_gated_clk_cell.v (DTM): pass-through upstream by default; with PDK_IHP130/PDK_ICS55/PDK_SKY130/ PDK_GF180 and without PDK_BEHAV they instantiate the process ICG cell (sg13g2_slgcp_1 with SCE, ICGX1H7R with the scan enable ORed into E because the ICS55 cell has no TE pin, sky130_fd_sc_hd__sdlclkp_1 with SCE, gf180mcu_fd_sc_mcu7t5v0__icgtp_1 with TE and notifier tied off). - BUFGCE.v (PLIC/CLINT div-2 gate): the upstream behavioral latch model stays byte-identical by default; the same four PDK branches substitute the process cell with the scan input tied off. The GF180 branch uses a repo-owned icgtp_1 functional model in rtl/tech/gf180_seq_sim_cells.v (following the file's dff precedent) because the vendor functional model references a UDP latch primitive that the locked gf180mcu-pdk checkout never ships. SKY130 picks up the vendor sdlclkp model through pdk_sky130.fl, following the existing cell pattern. ASIC CI profiles with PDK_BEHAV unset now compile real clock gating; PDK_BEHAV=YES profiles are bit-identical. Evidence: the manual's MEM_INTF c906_icg_test_tb passes on all four PDK cell paths (Icarus adaptation); the five-mode boot testbench suite passes on top of this change.
17 lines
1.1 KiB
Plaintext
17 lines
1.1 KiB
Plaintext
# SKY130 standard-cell models are selected by gen_iverilog_filelist.py.
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# Technology wrappers instantiate these functional models directly in RTL simulation.
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+define+FUNCTIONAL
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+incdir+/physical/pdk/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkbuf
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+incdir+/physical/pdk/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinv
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+incdir+/physical/pdk/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/mux2
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+incdir+/physical/pdk/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/xor2
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+incdir+/physical/pdk/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/sdlclkp
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/tech/sky130_io_sim_cells.v
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/clusterip/common/rtl/tech/ram.sv
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/tech/sky130_sram_sim_cells.sv
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/physical/pdk/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkbuf/sky130_fd_sc_hd__clkbuf_1.v
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/physical/pdk/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/clkinv/sky130_fd_sc_hd__clkinv_1.v
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/physical/pdk/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/mux2/sky130_fd_sc_hd__mux2_1.v
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/physical/pdk/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/xor2/sky130_fd_sc_hd__xor2_1.v
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/physical/pdk/skywater-pdk/libraries/sky130_fd_sc_hd/latest/cells/sdlclkp/sky130_fd_sc_hd__sdlclkp_1.v
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