mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-04 22:32:36 +00:00
maksyuki
65c19e7005
Complete the integration manual chapter 3 cell swap (the ICG half; the SRAM half landed earlier). Three new reviewed overrides, registered in generate_openc906.py with sha256 pins on the vendored files and added to the generated-filelist stamp prerequisites: - gated_clk_cell.v (216 CPU instances) and tdt_gated_clk_cell.v (DTM): pass-through upstream by default; with PDK_IHP130/PDK_ICS55/PDK_SKY130/ PDK_GF180 and without PDK_BEHAV they instantiate the process ICG cell (sg13g2_slgcp_1 with SCE, ICGX1H7R with the scan enable ORed into E because the ICS55 cell has no TE pin, sky130_fd_sc_hd__sdlclkp_1 with SCE, gf180mcu_fd_sc_mcu7t5v0__icgtp_1 with TE and notifier tied off). - BUFGCE.v (PLIC/CLINT div-2 gate): the upstream behavioral latch model stays byte-identical by default; the same four PDK branches substitute the process cell with the scan input tied off. The GF180 branch uses a repo-owned icgtp_1 functional model in rtl/tech/gf180_seq_sim_cells.v (following the file's dff precedent) because the vendor functional model references a UDP latch primitive that the locked gf180mcu-pdk checkout never ships. SKY130 picks up the vendor sdlclkp model through pdk_sky130.fl, following the existing cell pattern. ASIC CI profiles with PDK_BEHAV unset now compile real clock gating; PDK_BEHAV=YES profiles are bit-identical. Evidence: the manual's MEM_INTF c906_icg_test_tb passes on all four PDK cell paths (Icarus adaptation); the five-mode boot testbench suite passes on top of this change.
115 lines
2.5 KiB
Verilog
115 lines
2.5 KiB
Verilog
// retroSoC controlled override of the vendored OpenC906 BUFGCE.v.
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//
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// Source: openc906 dependency (dependencies.lock.json "openc906"),
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// C906_RTL_FACTORY/gen_rtl/common/rtl/BUFGCE.v
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// revision b0c06eb1f8b3bae663bd8b87eac89ff48e68a57f
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// License: Apache-2.0 (T-Head Semiconductor)
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//
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// retroSoC change (OpenC906 integration manual chapter 3 ICG swap): with a
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// PDK define and without PDK_BEHAV, the clock buffer-gate feeding the
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// PLIC/CLINT divide-by-2 domain (aq_mp_clk_top.v apb_clk_buf) uses the
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// process integrated clock-gating cell (same selection as
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// gated_clk_cell.v; there is no scan enable on this instance, so SCE/TE are
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// tied off). PDK_BEHAV and PDK-less builds keep the upstream behavioral
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// latch-based gate byte-identical. Keep in sync when the lock revision
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// changes.
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/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd.
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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module BUFGCE(
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I,
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CE,
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O
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);
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input I;
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input CE ;
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output O;
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`ifndef PDK_BEHAV
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`ifdef PDK_IHP130
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`define _AQ_BUFGCE_IHP130_
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`endif
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`ifdef PDK_ICS55
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`define _AQ_BUFGCE_ICS55_
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`endif
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`ifdef PDK_SKY130
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`define _AQ_BUFGCE_SKY130_
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`endif
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`ifdef PDK_GF180
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`define _AQ_BUFGCE_GF180_
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`endif
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`endif
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`ifdef _AQ_BUFGCE_IHP130_
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sg13g2_slgcp_1 u_icg (
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.CLK (I),
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.GATE (CE),
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.SCE (1'b0),
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.GCLK (O)
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);
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`elsif _AQ_BUFGCE_ICS55_
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ICGX1H7R u_icg (
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.CK (I),
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.E (CE),
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.ECK (O)
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);
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`elsif _AQ_BUFGCE_SKY130_
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sky130_fd_sc_hd__sdlclkp_1 u_icg (
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.CLK (I),
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.GATE (CE),
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.SCE (1'b0),
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.GCLK (O)
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);
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`elsif _AQ_BUFGCE_GF180_
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gf180mcu_fd_sc_mcu7t5v0__icgtp_1 u_icg (
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.CLK (I),
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.E (CE),
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.TE (1'b0),
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.Q (O),
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.notifier (1'b0)
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);
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`else
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reg clk_en_af_latch;
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always @(I or CE)
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begin
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if(!I)
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clk_en_af_latch <= CE;
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end
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reg clk_en ;
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always @ (clk_en_af_latch )
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begin
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clk_en <= clk_en_af_latch;
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end
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assign O = I && clk_en ;
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`endif
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`ifdef _AQ_BUFGCE_IHP130_
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`undef _AQ_BUFGCE_IHP130_
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`endif
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`ifdef _AQ_BUFGCE_ICS55_
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`undef _AQ_BUFGCE_ICS55_
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`endif
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`ifdef _AQ_BUFGCE_SKY130_
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`undef _AQ_BUFGCE_SKY130_
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`endif
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`ifdef _AQ_BUFGCE_GF180_
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`undef _AQ_BUFGCE_GF180_
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`endif
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endmodule
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