mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-04 22:32:36 +00:00
maksyuki
65c19e7005
Complete the integration manual chapter 3 cell swap (the ICG half; the SRAM half landed earlier). Three new reviewed overrides, registered in generate_openc906.py with sha256 pins on the vendored files and added to the generated-filelist stamp prerequisites: - gated_clk_cell.v (216 CPU instances) and tdt_gated_clk_cell.v (DTM): pass-through upstream by default; with PDK_IHP130/PDK_ICS55/PDK_SKY130/ PDK_GF180 and without PDK_BEHAV they instantiate the process ICG cell (sg13g2_slgcp_1 with SCE, ICGX1H7R with the scan enable ORed into E because the ICS55 cell has no TE pin, sky130_fd_sc_hd__sdlclkp_1 with SCE, gf180mcu_fd_sc_mcu7t5v0__icgtp_1 with TE and notifier tied off). - BUFGCE.v (PLIC/CLINT div-2 gate): the upstream behavioral latch model stays byte-identical by default; the same four PDK branches substitute the process cell with the scan input tied off. The GF180 branch uses a repo-owned icgtp_1 functional model in rtl/tech/gf180_seq_sim_cells.v (following the file's dff precedent) because the vendor functional model references a UDP latch primitive that the locked gf180mcu-pdk checkout never ships. SKY130 picks up the vendor sdlclkp model through pdk_sky130.fl, following the existing cell pattern. ASIC CI profiles with PDK_BEHAV unset now compile real clock gating; PDK_BEHAV=YES profiles are bit-identical. Evidence: the manual's MEM_INTF c906_icg_test_tb passes on all four PDK cell paths (Icarus adaptation); the five-mode boot testbench suite passes on top of this change.
74 lines
2.5 KiB
Verilog
74 lines
2.5 KiB
Verilog
// Copyright (c) 2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
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// retroSoC is licensed under Mulan PSL v2.
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// You can use this software according to the terms and conditions of the Mulan PSL v2.
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// You may obtain a copy of Mulan PSL v2 at:
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// http://license.coscl.org.cn/MulanPSL2
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// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
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// EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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// MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.
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// See the Mulan PSL v2 for more details.
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// You may use this software according to the terms and conditions of the Mulan PSL v2.
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// You may obtain a copy of Mulan PSL v2 at:
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// http://license.coscl.org.cn/MulanPSL2
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// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
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// EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
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// MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.
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// See the Mulan PSL v2 for more details.
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// Icarus functional models for the sequential GF180 cells selected by Yosys.
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// The upstream models expose a timing notifier that the synthesized netlist
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// leaves unconnected; these models retain the PDK cell interfaces without
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// propagating that high-impedance notifier into functional simulation.
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module gf180mcu_fd_sc_mcu7t5v0__dffq_1 (
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input wire CLK,
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input wire D,
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output reg Q,
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input wire notifier
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);
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always @(posedge CLK) Q <= D;
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endmodule
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module gf180mcu_fd_sc_mcu7t5v0__dffrnq_1 (
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input wire CLK,
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input wire D,
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input wire RN,
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output reg Q,
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input wire notifier
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);
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always @(posedge CLK or negedge RN) begin
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if (!RN) Q <= 1'b0;
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else Q <= D;
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end
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endmodule
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module gf180mcu_fd_sc_mcu7t5v0__dffsnq_1 (
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input wire CLK,
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input wire D,
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input wire SETN,
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output reg Q,
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input wire notifier
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);
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always @(posedge CLK or negedge SETN) begin
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if (!SETN) Q <= 1'b1;
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else Q <= D;
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end
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endmodule
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// The upstream icgtp functional model references a UDP latch primitive
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// (UDP_GF018hv5v_mcu_sc7_TT_1P8V_25C_verilog_nonpg_MGM_N_IQ_LATCH_UDP) that
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// is not shipped anywhere in the locked GF180 checkout, so the vendor model
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// cannot elaborate; this functional model retains the PDK cell interface.
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module gf180mcu_fd_sc_mcu7t5v0__icgtp_1 (
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input wire TE,
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input wire E,
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input wire CLK,
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output wire Q,
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input wire notifier
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);
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reg s_en_latch;
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always @(CLK or E or TE) begin
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if (!CLK) s_en_latch <= E | TE;
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end
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assign Q = CLK & s_en_latch;
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endmodule
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