mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-04 22:32:36 +00:00
maksyuki
67281e224f
- Introduced new test cases for APU-P3 loader, control store, and sequencer functionality in . - Enhanced the APU ring scheduler and stream router testbenches to validate reset timing and state transitions. - Added comprehensive tests for APU microcode tools, ensuring assembler and interpreter consistency. - Updated register parity tests to synchronize APU RTL and SDK ABI across P3. - Expanded formal filelist generation to include APU loader and sequencer. - Improved SBY configuration for formal verification with Bitwuzla.
462 lines
21 KiB
Systemverilog
462 lines
21 KiB
Systemverilog
// Copyright (c) 2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
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// retroSoC is licensed under Mulan PSL v2.
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`ifndef RETROSOC_APU_DEFINE_SVH
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`define RETROSOC_APU_DEFINE_SVH
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// verilog_format: off -- keep the handwritten hardware/software ABI column aligned
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`define APB4_APU__IP_ID 12'h000
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`define APB4_APU__IP_VERSION 12'h004
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`define APB4_APU__CAPABILITY0 12'h008
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`define APB4_APU__CAPABILITY1 12'h00c
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`define APB4_APU__COMMAND 12'h010
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`define APB4_APU__STATUS 12'h014
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`define APB4_APU__IRQ_STATE 12'h018
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`define APB4_APU__IRQ_ENABLE 12'h01c
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`define APB4_APU__IRQ_TEST 12'h020
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`define APB4_APU__ERROR_STATUS 12'h024
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`define APB4_APU__ERROR_ADDRESS 12'h028
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`define APB4_APU__ERROR_DETAIL 12'h02c
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`define APB4_APU__SEQUENCER_TIMEOUT 12'h030
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`define APB4_APU__STREAM_ROUTE 12'h034
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`define APB4_APU__STREAM_STATUS 12'h038
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`define APB4_APU__OWNER_STATUS 12'h03c
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`define APB4_APU__READ_BASE 12'h040
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`define APB4_APU__READ_LIMIT 12'h044
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`define APB4_APU__WRITE_BASE 12'h048
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`define APB4_APU__WRITE_LIMIT 12'h04c
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`define APB4_APU__DMA_TIMEOUT 12'h050
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`define APB4_APU__ABI_DIGEST 12'h054
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`define APB4_APU__SEQUENCER_STATUS 12'h058
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`define APB4_APU__SEQUENCER_RETIRED 12'h05c
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`define APB4_APU__STREAM_WATERMARK 12'h060
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`define APB4_APU__MC_IMAGE_ADDRESS 12'h080
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`define APB4_APU__MC_IMAGE_SIZE 12'h084
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`define APB4_APU__MC_EXPECTED_CRC 12'h088
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`define APB4_APU__MC_STATUS 12'h08c
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`define APB4_APU__MC_ABI 12'h090
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`define APB4_APU__MC_BUILD_ID_LO 12'h094
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`define APB4_APU__MC_BUILD_ID_HI 12'h098
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`define APB4_APU__MC_LOCK 12'h09c
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`define APB4_APU__MC_ACTUAL_CRC 12'h0a0
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`define APB4_APU__MC_LOAD_COUNT 12'h0a4
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`define APB4_APU__JOB_CONTROL 12'h100
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`define APB4_APU__JOB_INPUT_ADDRESS 12'h104
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`define APB4_APU__JOB_INPUT_LENGTH 12'h108
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`define APB4_APU__JOB_OUTPUT_ADDRESS 12'h10c
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`define APB4_APU__JOB_OUTPUT_CAPACITY 12'h110
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`define APB4_APU__JOB_INPUT_CONFIG 12'h114
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`define APB4_APU__JOB_OUTPUT_CONFIG 12'h118
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`define APB4_APU__JOB_FLAGS 12'h11c
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`define APB4_APU__JOB_STATUS 12'h120
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`define APB4_APU__JOB_INPUT_USED 12'h124
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`define APB4_APU__JOB_OUTPUT_BYTES 12'h128
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`define APB4_APU__JOB_FRAMES 12'h12c
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`define APB4_APU__JOB_SOURCE_INFO 12'h130
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`define APB4_APU__JOB_CYCLES 12'h134
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`define APB4_APU__JOB_DETAIL 12'h138
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`define APB4_APU__RING_BASE 12'h180
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`define APB4_APU__RING_SIZE 12'h184
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`define APB4_APU__RING_HEAD 12'h188
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`define APB4_APU__RING_TAIL 12'h18c
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`define APB4_APU__RING_CONTROL 12'h190
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`define APB4_APU__RING_STATUS 12'h194
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`define APB4_APU__RING_COMPLETED 12'h198
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`define APB4_APU__RING_COALESCE 12'h19c
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`define APB4_APU__RING_DOORBELL 12'h1a0
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`define APB4_APU__KWS_MODEL_ADDRESS 12'h200
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`define APB4_APU__KWS_MODEL_SIZE 12'h204
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`define APB4_APU__KWS_MODEL_EXPECTED_CRC 12'h208
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`define APB4_APU__KWS_CONTROL 12'h20c
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`define APB4_APU__KWS_CONFIG 12'h210
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`define APB4_APU__KWS_STATUS 12'h214
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`define APB4_APU__KWS_RESULT 12'h218
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`define APB4_APU__KWS_TIMESTAMP_LO 12'h21c
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`define APB4_APU__KWS_TIMESTAMP_HI 12'h220
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`define APB4_APU__KWS_FRAME_COUNT 12'h224
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`define APB4_APU__KWS_INFERENCE_COUNT 12'h228
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`define APB4_APU__KWS_HIT_COUNT 12'h22c
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`define APB4_APU__KWS_OVERRUN_COUNT 12'h230
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`define APB4_APU__KWS_MODEL_STATUS 12'h234
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`define APB4_APU__KWS_MODEL_ACTUAL_CRC 12'h238
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`define APB4_APU__PERF_CONTROL 12'h300
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`define APB4_APU__PERF_STATUS 12'h304
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`define APB4_APU__PERF_ACTIVE_CYCLES_LO 12'h308
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`define APB4_APU__PERF_ACTIVE_CYCLES_HI 12'h30c
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`define APB4_APU__PERF_INPUT_BYTES_LO 12'h310
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`define APB4_APU__PERF_INPUT_BYTES_HI 12'h314
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`define APB4_APU__PERF_OUTPUT_BYTES_LO 12'h318
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`define APB4_APU__PERF_OUTPUT_BYTES_HI 12'h31c
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`define APB4_APU__PERF_DECODED_FRAMES_LO 12'h320
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`define APB4_APU__PERF_DECODED_FRAMES_HI 12'h324
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`define APB4_APU__PERF_DMA_READ_STALLS_LO 12'h328
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`define APB4_APU__PERF_DMA_READ_STALLS_HI 12'h32c
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`define APB4_APU__PERF_DMA_WRITE_STALLS_LO 12'h330
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`define APB4_APU__PERF_DMA_WRITE_STALLS_HI 12'h334
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`define APB4_APU__PERF_STREAM_STALLS_LO 12'h338
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`define APB4_APU__PERF_STREAM_STALLS_HI 12'h33c
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`define APB4_APU__PERF_SEQUENCER_INSTR_LO 12'h340
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`define APB4_APU__PERF_SEQUENCER_INSTR_HI 12'h344
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`define APB4_APU__PERF_KWS_CYCLES_LO 12'h348
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`define APB4_APU__PERF_KWS_CYCLES_HI 12'h34c
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`define APB4_APU__PERF_FAULTS_LO 12'h350
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`define APB4_APU__PERF_FAULTS_HI 12'h354
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`define APB4_APU__CAPABILITY0_WAV 0
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`define APB4_APU__CAPABILITY0_MP3 1
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`define APB4_APU__CAPABILITY0_FLAC 2
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`define APB4_APU__CAPABILITY0_PRIVATE_DMA 3
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`define APB4_APU__CAPABILITY0_RING 4
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`define APB4_APU__CAPABILITY0_STREAMS 5
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`define APB4_APU__CAPABILITY0_KWS 6
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`define APB4_APU__CAPABILITY0_SEQUENCER 7
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`define APB4_APU__CAPABILITY0_RESAMPLER 8
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`define APB4_APU__CAPABILITY1_CONTROL_KIB 0
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`define APB4_APU__CAPABILITY1_DATA_KIB 8
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`define APB4_APU__CAPABILITY1_MAX_CHANNELS 16
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`define APB4_APU__CAPABILITY1_MAX_RATE_KHZ 18
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`define APB4_APU__COMMAND_START_DIRECT 0
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`define APB4_APU__COMMAND_ABORT 1
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`define APB4_APU__COMMAND_SOFT_RESET 2
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`define APB4_APU__COMMAND_RING_KICK 3
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`define APB4_APU__COMMAND_MICROCODE_LOAD 4
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`define APB4_APU__COMMAND_MODEL_LOAD 5
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`define APB4_APU__COMMAND_CLEAR_COUNTERS 6
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`define APB4_APU__STATUS_MICROCODE_VALID 0
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`define APB4_APU__STATUS_MODEL_VALID 1
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`define APB4_APU__STATUS_BUSY 2
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`define APB4_APU__STATUS_RING 3
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`define APB4_APU__STATUS_DECODE 4
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`define APB4_APU__STATUS_KWS_LISTENING 5
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`define APB4_APU__STATUS_QUIESCED 6
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`define APB4_APU__STATUS_ABORTING 7
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`define APB4_APU__STATUS_IDLE 8
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`define APB4_APU__STATUS_SEQUENCER_TRAPPED 9
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`define APB4_APU__STREAM_STATUS_TX_ACTIVE 0
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`define APB4_APU__STREAM_STATUS_RX_ACTIVE 1
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`define APB4_APU__STREAM_STATUS_TX_EMPTY 2
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`define APB4_APU__STREAM_STATUS_TX_FULL 3
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`define APB4_APU__STREAM_STATUS_RX_EMPTY 4
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`define APB4_APU__STREAM_STATUS_RX_FULL 5
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`define APB4_APU__STREAM_STATUS_TX_UNDERRUN 6
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`define APB4_APU__STREAM_STATUS_RX_OVERRUN 7
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`define APB4_APU__STREAM_STATUS_TX_COUNT 8
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`define APB4_APU__STREAM_STATUS_RX_COUNT 16
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`define APB4_APU__STREAM_WATERMARK_RX_HIGH 0
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`define APB4_APU__STREAM_WATERMARK_TX_LOW 8
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`define APB4_APU__IRQ_DIRECT_DONE 0
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`define APB4_APU__IRQ_RING_EVENT 1
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`define APB4_APU__IRQ_KWS_HIT 2
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`define APB4_APU__IRQ_MICROCODE_LOAD_DONE 3
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`define APB4_APU__IRQ_MODEL_LOAD_DONE 4
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`define APB4_APU__IRQ_ABORT_DONE 5
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`define APB4_APU__IRQ_INPUT_WATERMARK 6
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`define APB4_APU__IRQ_OUTPUT_WATERMARK 7
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`define APB4_APU__IRQ_FIRST_ERROR 8
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`define APB4_APU__IRQ_STREAM_XRUN 9
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`define APB4_APU__IRQ_SEQUENCER_TRAP 10
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`define APB4_APU__ERROR_VALID 0
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`define APB4_APU__ERROR_CODE 1
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`define APB4_APU__ERROR_STAGE 7
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`define APB4_APU__ERROR_AXI_RESPONSE 11
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`define APB4_APU__ERROR_DESCRIPTOR_INDEX 13
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`define APB4_APU__ERROR_CODE_NONE 0
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`define APB4_APU__ERROR_CODE_INVALID_CONFIG 1
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`define APB4_APU__ERROR_CODE_INVALID_RING 2
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`define APB4_APU__ERROR_CODE_UNSUPPORTED 3
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`define APB4_APU__ERROR_CODE_MALFORMED 4
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`define APB4_APU__ERROR_CODE_TRUNCATED 5
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`define APB4_APU__ERROR_CODE_CODEC_CRC 6
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`define APB4_APU__ERROR_CODE_DECODE 7
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`define APB4_APU__ERROR_CODE_RECONSTRUCTION 8
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`define APB4_APU__ERROR_CODE_MICROCODE 9
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`define APB4_APU__ERROR_CODE_MICROCODE_CRC 10
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`define APB4_APU__ERROR_CODE_SEQUENCER 11
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`define APB4_APU__ERROR_CODE_KWS_MODEL 12
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`define APB4_APU__ERROR_CODE_KWS_CRC 13
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`define APB4_APU__ERROR_CODE_KWS_ARITHMETIC 14
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`define APB4_APU__ERROR_CODE_AXI_READ 15
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`define APB4_APU__ERROR_CODE_AXI_WRITE 16
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`define APB4_APU__ERROR_CODE_DMA_TIMEOUT 17
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`define APB4_APU__ERROR_CODE_STREAM_UNDERRUN 18
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`define APB4_APU__ERROR_CODE_STREAM_OVERRUN 19
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`define APB4_APU__ERROR_CODE_ABORT 20
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`define APB4_APU__ERROR_CODE_RESOURCE_RESET 21
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`define APB4_APU__ERROR_CODE_OVERFLOW 22
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`define APB4_APU__ERROR_STAGE_APB 0
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`define APB4_APU__ERROR_STAGE_LOADER 1
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`define APB4_APU__ERROR_STAGE_RING 2
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`define APB4_APU__ERROR_STAGE_DMA_READ 3
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`define APB4_APU__ERROR_STAGE_BITSTREAM 4
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`define APB4_APU__ERROR_STAGE_ENTROPY 5
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`define APB4_APU__ERROR_STAGE_RECONSTRUCTION 6
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`define APB4_APU__ERROR_STAGE_RESAMPLER 7
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`define APB4_APU__ERROR_STAGE_DMA_WRITE 8
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`define APB4_APU__ERROR_STAGE_KWS_FRONTEND 9
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`define APB4_APU__ERROR_STAGE_KWS_INFERENCE 10
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`define APB4_APU__ERROR_STAGE_LIFECYCLE 11
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`define APB4_APU__OWNER_STATUS_OWNER 0
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`define APB4_APU__OWNER_STATUS_LOCK 8
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`define APB4_APU__OWNER_STATUS_QUIESCE 9
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`define APB4_APU__OWNER_STATUS_RESET 10
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`define APB4_APU__JOB_STATUS_BUSY 0
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`define APB4_APU__JOB_STATUS_DONE 1
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`define APB4_APU__JOB_STATUS_ERROR 2
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`define APB4_APU__JOB_STATUS_ABORTED 3
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`define APB4_APU__JOB_STATUS_DIRECT_ACTIVE 4
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`define APB4_APU__JOB_STATUS_INPUT_PENDING 5
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`define APB4_APU__JOB_STATUS_OUTPUT_PENDING 6
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`define APB4_APU__JOB_STATUS_WRITEBACK_PENDING 7
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`define APB4_APU__JOB_STATUS_ERROR_CODE 8
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`define APB4_APU__JOB_STATUS_STAGE 14
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`define APB4_APU__JOB_STATUS_AXI_RESPONSE 18
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`define APB4_APU__RING_STATUS_ACTIVE 0
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`define APB4_APU__RING_STATUS_STALLED_UNOWNED 1
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`define APB4_APU__RING_STATUS_EMPTY 2
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`define APB4_APU__RING_STATUS_ERROR 3
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`define APB4_APU__RING_STATUS_WRAPPED 4
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`define APB4_APU__RING_STATUS_COALESCE_PENDING 5
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`define APB4_APU__RING_STATUS_WRITEBACK_PENDING 6
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`define APB4_APU__RING_STATUS_STOPPED_ON_ERROR 7
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`define APB4_APU__RING_STATUS_PENDING_COUNT 8
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`define APB4_APU__RING_STATUS_LAST_INDEX 16
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`define APB4_APU__DESCRIPTOR_WORDS 32
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`define APB4_APU__DESCRIPTOR_BYTES 128
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`define APB4_APU__DESCRIPTOR_ALIGNMENT 128
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`define APB4_APU__DESCRIPTOR_CONTROL 0
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`define APB4_APU__DESCRIPTOR_RESULT_STATUS 1
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`define APB4_APU__DESCRIPTOR_INPUT_ADDRESS 2
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`define APB4_APU__DESCRIPTOR_INPUT_LENGTH 3
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`define APB4_APU__DESCRIPTOR_OUTPUT_ADDRESS 4
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`define APB4_APU__DESCRIPTOR_OUTPUT_CAPACITY 5
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`define APB4_APU__DESCRIPTOR_INPUT_CONFIG 6
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`define APB4_APU__DESCRIPTOR_OUTPUT_CONFIG 7
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`define APB4_APU__DESCRIPTOR_JOB_FLAGS 8
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`define APB4_APU__DESCRIPTOR_KWS_CONFIG 9
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`define APB4_APU__DESCRIPTOR_RESULT_INPUT_USED 10
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`define APB4_APU__DESCRIPTOR_RESULT_OUTPUT_BYTES 11
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`define APB4_APU__DESCRIPTOR_RESULT_FRAMES 12
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`define APB4_APU__DESCRIPTOR_RESULT_SOURCE_INFO 13
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`define APB4_APU__DESCRIPTOR_RESULT_CYCLES 14
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`define APB4_APU__DESCRIPTOR_RESULT_DETAIL 15
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`define APB4_APU__DESCRIPTOR_COOKIE_LO 16
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`define APB4_APU__DESCRIPTOR_COOKIE_HI 17
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`define APB4_APU__DESCRIPTOR_START_TIMESTAMP_LO 18
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`define APB4_APU__DESCRIPTOR_START_TIMESTAMP_HI 19
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`define APB4_APU__DESCRIPTOR_FINISH_TIMESTAMP_LO 20
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`define APB4_APU__DESCRIPTOR_FINISH_TIMESTAMP_HI 21
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`define APB4_APU__DESCRIPTOR_KWS_RESULT 22
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`define APB4_APU__DESCRIPTOR_MICROCODE_BUILD_ID 23
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`define APB4_APU__DESCRIPTOR_CONTROL_OPERATION 0
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`define APB4_APU__DESCRIPTOR_CONTROL_INPUT_FORMAT 4
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`define APB4_APU__DESCRIPTOR_CONTROL_OUTPUT_MODE 8
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`define APB4_APU__DESCRIPTOR_CONTROL_DOWNMIX 10
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`define APB4_APU__DESCRIPTOR_CONTROL_RESAMPLE 11
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`define APB4_APU__DESCRIPTOR_CONTROL_IOC 30
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`define APB4_APU__DESCRIPTOR_CONTROL_OWN 31
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`define APB4_APU__DESCRIPTOR_STATUS_DONE 0
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`define APB4_APU__DESCRIPTOR_STATUS_ERROR 1
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`define APB4_APU__DESCRIPTOR_STATUS_ABORTED 2
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`define APB4_APU__DESCRIPTOR_STATUS_ERROR_CODE 3
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`define APB4_APU__DESCRIPTOR_STATUS_STAGE 9
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`define APB4_APU__DESCRIPTOR_STATUS_AXI_RESPONSE 13
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`define APB4_APU__PERF_CONTROL_ENABLE 0
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`define APB4_APU__PERF_CONTROL_CLEAR 1
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`define APB4_APU__PERF_CONTROL_SNAPSHOT 2
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`define APB4_APU__PERF_STATUS_SNAPSHOT_VALID 0
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`define APB4_APU__MC_STATUS_BUSY 0
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`define APB4_APU__MC_STATUS_VALID 1
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`define APB4_APU__MC_STATUS_HEADER_ERROR 2
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`define APB4_APU__MC_STATUS_RANGE_ERROR 3
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`define APB4_APU__MC_STATUS_CONTROL_ERROR 4
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`define APB4_APU__MC_STATUS_TABLE_ERROR 5
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`define APB4_APU__MC_STATUS_CRC_ERROR 6
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`define APB4_APU__MC_STATUS_CAPABILITY_ERROR 7
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`define APB4_APU__MC_LOCK_LOCKED 0
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`define APB4_APU__SEQUENCER_STATUS_PC 0
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`define APB4_APU__SEQUENCER_STATUS_CLASS 11
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`define APB4_APU__SEQUENCER_STATUS_OPCODE 15
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`define APB4_APU__SEQUENCER_STATUS_WAIT 19
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`define APB4_APU__SEQUENCER_STATUS_LOOP 20
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`define APB4_APU__APUMC_MAGIC 32'h4150_4d43
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`define APB4_APU__APUMC_ABI 32'h0001_0000
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`define APB4_APU__APUMC_HEADER_BYTES 64
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`define APB4_APU__APUMC_HEADER_WORDS 16
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`define APB4_APU__APUMC_ENTRY_BYTES 32
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`define APB4_APU__APUMC_ENTRY_WORDS 8
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`define APB4_APU__APUMC_ENTRY_COUNT 3
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`define APB4_APU__APUMC_MAX_INSTRUCTIONS 2048
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`define APB4_APU__APUMC_HEADER_MAGIC 0
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`define APB4_APU__APUMC_HEADER_ABI 1
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`define APB4_APU__APUMC_HEADER_TOTAL_BYTES 2
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`define APB4_APU__APUMC_HEADER_INSTRUCTIONS 3
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`define APB4_APU__APUMC_HEADER_INSTR_OFFSET 4
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`define APB4_APU__APUMC_HEADER_TABLE_OFFSET 5
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`define APB4_APU__APUMC_HEADER_TABLE_BYTES 6
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`define APB4_APU__APUMC_HEADER_ENTRY_OFFSET 7
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`define APB4_APU__APUMC_HEADER_ENTRY_COUNT 8
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`define APB4_APU__APUMC_HEADER_PRIMITIVES 9
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`define APB4_APU__APUMC_HEADER_SCRATCH_END 10
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`define APB4_APU__APUMC_HEADER_CRC 11
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`define APB4_APU__APUMC_HEADER_BUILD_LO 12
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`define APB4_APU__APUMC_HEADER_BUILD_HI 13
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`define APB4_APU__APUMC_ENTRY_FORMAT_PC 0
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`define APB4_APU__APUMC_ENTRY_RANGE 1
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`define APB4_APU__APUMC_ENTRY_SCRATCH_BASE 2
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`define APB4_APU__APUMC_ENTRY_SCRATCH_BYTES 3
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`define APB4_APU__APUMC_ENTRY_MAX_LOOP 4
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`define APB4_APU__APUMC_ENTRY_MAX_RETIRED 5
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`define APB4_APU__APUMC_ENTRY_PRIMITIVES 6
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`define APB4_APU__APUMC_ENTRY_TABLE 7
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`define APB4_APU__MC_INSTRUCTION_IMMEDIATE 0
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`define APB4_APU__MC_INSTRUCTION_AUX 32
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`define APB4_APU__MC_INSTRUCTION_SRC1 40
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`define APB4_APU__MC_INSTRUCTION_SRC0 44
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`define APB4_APU__MC_INSTRUCTION_DST 48
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`define APB4_APU__MC_INSTRUCTION_PREDICATE 52
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`define APB4_APU__MC_INSTRUCTION_OPCODE 56
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`define APB4_APU__MC_INSTRUCTION_CLASS 60
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`define APB4_APU__MC_CLASS_CONTROL 0
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`define APB4_APU__MC_CLASS_SCALAR 1
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`define APB4_APU__MC_CLASS_BITSTREAM 2
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`define APB4_APU__MC_CLASS_ENTROPY 3
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`define APB4_APU__MC_CLASS_LOCAL 4
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`define APB4_APU__MC_CLASS_KERNEL 5
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`define APB4_APU__MC_CLASS_TRANSPORT 6
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`define APB4_APU__MC_CONTROL_NOP 0
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`define APB4_APU__MC_CONTROL_END 1
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`define APB4_APU__MC_CONTROL_TRAP 2
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`define APB4_APU__MC_CONTROL_JUMP_FWD 3
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`define APB4_APU__MC_CONTROL_CALL_FWD 4
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`define APB4_APU__MC_CONTROL_RET 5
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`define APB4_APU__MC_CONTROL_LOOP_SETUP 6
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`define APB4_APU__MC_CONTROL_LOOP_BACK 7
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`define APB4_APU__MC_CONTROL_WAIT 8
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`define APB4_APU__MC_SCALAR_MOV 0
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`define APB4_APU__MC_SCALAR_MOVI 1
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`define APB4_APU__MC_SCALAR_ADD 2
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`define APB4_APU__MC_SCALAR_SUB 3
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`define APB4_APU__MC_SCALAR_AND 4
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`define APB4_APU__MC_SCALAR_OR 5
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`define APB4_APU__MC_SCALAR_XOR 6
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`define APB4_APU__MC_SCALAR_SHL 7
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`define APB4_APU__MC_SCALAR_SHR 8
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`define APB4_APU__MC_SCALAR_SAR 9
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`define APB4_APU__MC_SCALAR_CMP 10
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`define APB4_APU__MC_SCALAR_MIN 11
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`define APB4_APU__MC_SCALAR_MAX 12
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`define APB4_APU__MC_SCALAR_SAT 13
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`define APB4_APU__MC_BITSTREAM_REFILL 0
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`define APB4_APU__MC_BITSTREAM_PEEK 1
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`define APB4_APU__MC_BITSTREAM_GET 2
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`define APB4_APU__MC_BITSTREAM_SKIP 3
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`define APB4_APU__MC_BITSTREAM_ALIGN 4
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`define APB4_APU__MC_BITSTREAM_FRAME_SYNC 5
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`define APB4_APU__MC_BITSTREAM_CRC8 6
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`define APB4_APU__MC_BITSTREAM_CRC16 7
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`define APB4_APU__MC_ENTROPY_HUFF_SYMBOL 0
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`define APB4_APU__MC_ENTROPY_HUFF_PAIR 1
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`define APB4_APU__MC_ENTROPY_HUFF_QUAD 2
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`define APB4_APU__MC_ENTROPY_UNARY 3
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`define APB4_APU__MC_ENTROPY_RICE4 4
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`define APB4_APU__MC_ENTROPY_RICE5 5
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`define APB4_APU__MC_ENTROPY_SIGN_RESTORE 6
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`define APB4_APU__MC_LOCAL_LD32 0
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`define APB4_APU__MC_LOCAL_ST32 1
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`define APB4_APU__MC_LOCAL_TABLE8 2
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`define APB4_APU__MC_LOCAL_TABLE16 3
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`define APB4_APU__MC_LOCAL_TABLE32 4
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`define APB4_APU__MC_LOCAL_FIFO_POP 5
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`define APB4_APU__MC_LOCAL_FIFO_PUSH 6
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`define APB4_APU__MC_KERNEL_REQUANT 0
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`define APB4_APU__MC_KERNEL_STEREO 1
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`define APB4_APU__MC_KERNEL_IMDCT6 2
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`define APB4_APU__MC_KERNEL_IMDCT18 3
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`define APB4_APU__MC_KERNEL_DCT32_POLY 4
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`define APB4_APU__MC_KERNEL_FIXED 5
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`define APB4_APU__MC_KERNEL_LPC 6
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`define APB4_APU__MC_KERNEL_DECORRELATE 7
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`define APB4_APU__MC_KERNEL_RESAMPLE 8
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`define APB4_APU__MC_KERNEL_PCM_PACK 9
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`define APB4_APU__MC_TRANSPORT_INPUT_REFILL 0
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`define APB4_APU__MC_TRANSPORT_OUTPUT_COMMIT 1
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`define APB4_APU__MC_TRANSPORT_OUTPUT_STREAM 2
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`define APB4_APU__MC_TRANSPORT_DMA_WAIT 3
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`define APB4_APU__MC_TRANSPORT_FRAME_COMMIT 4
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`define APB4_APU__MC_TRANSPORT_JOB_RESULT 5
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`define APB4_APU__MC_TRANSPORT_EVENT 6
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`define APB4_APU__MC_PRED_ALWAYS 0
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`define APB4_APU__MC_PRED_EQ 1
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`define APB4_APU__MC_PRED_NE 2
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`define APB4_APU__MC_PRED_SIGNED_LT 3
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`define APB4_APU__MC_PRED_SIGNED_GE 4
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`define APB4_APU__MC_PRED_UNSIGNED_LT 5
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`define APB4_APU__MC_PRED_UNSIGNED_GE 6
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`define APB4_APU__MC_PRED_INPUT_EXHAUSTED 7
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`define APB4_APU__MC_PRED_INPUT_READY 8
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`define APB4_APU__MC_PRED_OUTPUT_READY 9
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`define APB4_APU__MC_PRED_KERNEL_DONE 10
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`define APB4_APU__MC_PRED_TRANSPORT_DONE 11
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`define APB4_APU__MC_WAIT_DMA 0
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`define APB4_APU__MC_WAIT_KERNEL 1
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|
`define APB4_APU__MC_WAIT_INPUT_FIFO 2
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`define APB4_APU__MC_WAIT_OUTPUT_FIFO 3
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`define APB4_APU__MC_WAIT_TX_STREAM 4
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`define APB4_APU__MC_WAIT_RING_WRITEBACK 5
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`define APB4_APU__MC_PRIMITIVE_BITSTREAM 0
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`define APB4_APU__MC_PRIMITIVE_CRC 1
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`define APB4_APU__MC_PRIMITIVE_HUFFMAN 2
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`define APB4_APU__MC_PRIMITIVE_RICE 3
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`define APB4_APU__MC_PRIMITIVE_LOCAL_MEMORY 4
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|
`define APB4_APU__MC_PRIMITIVE_LOCAL_FIFO 5
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`define APB4_APU__MC_PRIMITIVE_REQUANTIZE 6
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`define APB4_APU__MC_PRIMITIVE_STEREO 7
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`define APB4_APU__MC_PRIMITIVE_IMDCT6 8
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`define APB4_APU__MC_PRIMITIVE_IMDCT18 9
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`define APB4_APU__MC_PRIMITIVE_DCT32_POLY 10
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`define APB4_APU__MC_PRIMITIVE_FIXED 11
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`define APB4_APU__MC_PRIMITIVE_LPC 12
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`define APB4_APU__MC_PRIMITIVE_DECORRELATE 13
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`define APB4_APU__MC_PRIMITIVE_RESAMPLER 14
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`define APB4_APU__MC_PRIMITIVE_PCM_PACK 15
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`define APB4_APU__MC_PRIMITIVE_DMA_INPUT 16
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`define APB4_APU__MC_PRIMITIVE_DMA_OUTPUT 17
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`define APB4_APU__MC_PRIMITIVE_STREAM_OUTPUT 18
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`define APB4_APU__MC_PRIMITIVE_FRAME_COMMIT 19
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|
`define APB4_APU__MC_PRIMITIVE_EVENT 20
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|
`define APB4_APU__MC_TRAP_ILLEGAL 1
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|
`define APB4_APU__MC_TRAP_PC_RANGE 2
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|
`define APB4_APU__MC_TRAP_CALL_STACK 3
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|
`define APB4_APU__MC_TRAP_LOOP 4
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`define APB4_APU__MC_TRAP_LOCAL_RANGE 5
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`define APB4_APU__MC_TRAP_UNAVAILABLE 6
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`define APB4_APU__MC_TRAP_WATCHDOG 7
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`define APB4_APU__MC_TRAP_RETIRED_BUDGET 8
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`define APB4_APU__MC_TRAP_ENGINE 9
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|
`define APB4_APU__MC_TRAP_EXPLICIT 10
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// verilog_format: on
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|
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`endif
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