mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-04 22:32:36 +00:00
maksyuki
67281e224f
- Introduced new test cases for APU-P3 loader, control store, and sequencer functionality in . - Enhanced the APU ring scheduler and stream router testbenches to validate reset timing and state transitions. - Added comprehensive tests for APU microcode tools, ensuring assembler and interpreter consistency. - Updated register parity tests to synchronize APU RTL and SDK ABI across P3. - Expanded formal filelist generation to include APU loader and sequencer. - Improved SBY configuration for formal verification with Bitwuzla.
79 lines
3.2 KiB
Systemverilog
79 lines
3.2 KiB
Systemverilog
// Copyright (c) 2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
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// SPDX-License-Identifier: MulanPSL-2.0
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module apu_loader_formal;
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(* anyseq *) (* gclk *) reg clk_i;
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wire rst_n_i, f_past_valid;
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wire [2:0] scenario;
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wire [1:0] request_count;
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wire [6:0] cycle;
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wire [7:0] status;
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wire lock, store_write, load_done, abort_done, fault_valid;
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wire abort_seen, fault_seen, load_seen, store_seen;
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wire [10:0] store_addr;
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wire [ 5:0] fault_code;
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wire [ 3:0] fault_stage;
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wire [ 1:0] fault_resp;
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wire [31:0] fault_addr, fault_detail, actual_crc;
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apu_loader_formal_design u_design (.*);
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always @(posedge clk_i) begin
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if (rst_n_i) begin
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assert (!(status[0] && (|status[7:1])));
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assert (request_count <= 2'd3);
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if (store_write) begin
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assert (status[0]);
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assert (request_count == 2'd3);
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assert (store_addr[10:0] == store_addr);
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end
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if (load_done) assert (status[1] && lock);
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if (abort_seen || fault_seen) assert (!status[1] && !lock && !load_seen);
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if (load_seen) assert (store_seen && status[1] && lock);
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if (scenario == 3'd0) begin
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assert (!fault_valid || (fault_code != 6'd9));
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end else if (scenario == 3'd1) begin
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if (fault_valid) begin
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assert (status[3] && !lock && !store_seen && (request_count == 2'd1));
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assert ((fault_code == 6'd9) && (fault_stage == 4'd1) && (fault_resp == 2'd0));
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assert ((fault_addr == 32'h0000_1014) && (fault_detail == 32'd204));
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assert (actual_crc == 32'd0);
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end
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end else if (scenario == 3'd2) begin
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if (fault_valid) begin
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assert (status[3] && !lock && !store_seen && (request_count == 2'd2));
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assert ((fault_code == 6'd9) && (fault_stage == 4'd1) && (fault_resp == 2'd0));
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assert ((fault_addr == 32'h0000_1054) && (fault_detail == 32'd0));
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assert (actual_crc == 32'd0);
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end
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end else if (scenario == 3'd3) begin
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if (fault_valid) begin
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assert (status[6] && !lock && (fault_code == 6'd10));
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assert ((fault_stage == 4'd1) && (fault_resp == 2'd0) && (fault_addr == 32'h0000_102c));
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end
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end else if (scenario == 3'd4) begin
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if (fault_valid) begin
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assert (status[4] && !lock && (fault_code == 6'd9));
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assert ((fault_stage == 4'd1) && (fault_resp == 2'd0) && (fault_addr == 32'h0000_10c0));
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assert (fault_detail[7:0] == 8'd3);
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end
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end else if (scenario == 3'd6) begin
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if (fault_valid) begin
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assert (!lock && (fault_code == 6'd21) && (fault_stage == 4'd11));
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end
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end
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end
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if (f_past_valid && $past(rst_n_i) && $past(status[0]) && !load_done) begin
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assert (!status[1]);
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end
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cover (rst_n_i &&
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(((scenario == 3'd0) && load_seen && store_seen && status[1] && lock) ||
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((scenario == 3'd1) && fault_valid && status[3]) ||
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((scenario == 3'd2) && fault_valid && status[3]) ||
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((scenario == 3'd3) && fault_valid && status[6]) ||
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((scenario == 3'd4) && fault_valid && status[4]) ||
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((scenario == 3'd5) && abort_seen) ||
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((scenario == 3'd6) && fault_seen)));
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end
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endmodule
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