mirror of
https://github.com/retroSoC/retroSoC.git
synced 2026-11-06 22:55:14 +00:00
maksyuki
6be73fa6b7
- Changed the interface from ribp to rib in soc_topology.json and related files. - Updated formal.mk to reflect the new rib2apb naming convention. - Implemented rib2apb module to handle RIB to APB communication. - Modified bus.sv to integrate the new rib2apb module and adjust signal assignments accordingly. - Updated testbench files to use the new rib interface and validate the RIB to APB functionality. - Created rib2apb_tb for testing the direct RIB to APB bridge. - Adjusted script tools and test scripts to accommodate the new naming and structure.
114 lines
3.8 KiB
Systemverilog
114 lines
3.8 KiB
Systemverilog
// Copyright (c) 2026 Yuchi Miao <miaoyuchi@ict.ac.cn>
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// retroSoC is licensed under Mulan PSL v2.
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// You can use this software according to the terms and conditions of the Mulan PSL v2.
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// You may obtain a copy of the Mulan PSL v2 at:
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// http://license.coscl.org.cn/MulanPSL2
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// THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
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// EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
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// MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.
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// See the Mulan PSL v2 for more details.
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module rib2apb_formal;
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localparam logic [2:0] FSM_ENAB = 3'd3;
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localparam logic [2:0] FSM_ERR = 3'd5;
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localparam logic [2:0] RIB_RESP_OK = 3'd0;
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localparam logic [2:0] RIB_RESP_SLVERR = 3'd3;
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(* anyseq *) (* gclk *)reg clk_i;
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wire rst_n_i;
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wire f_past_valid;
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wire rib_cmd_valid;
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wire [31:0] rib_cmd_addr;
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wire rib_cmd_write;
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wire [ 1:0] rib_cmd_len;
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wire rib_cmd_ready;
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wire rib_w_valid;
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wire [31:0] rib_wdata;
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wire [ 3:0] rib_wstrb;
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wire rib_wlast;
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wire rib_w_ready;
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wire rib_rsp_valid;
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wire [31:0] rib_rdata;
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wire rib_resp_err;
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wire [ 2:0] rib_resp_code;
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wire [ 1:0] rib_rsp_beat;
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wire rib_rsp_last;
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wire rib_rsp_ready;
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wire [ 9:0] psel_comb;
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wire [ 9:0] psel_q;
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wire xfer_ready;
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wire xfer_error;
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wire rsp_input_valid;
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wire rsp_input_ready;
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wire [38:0] rsp_input_data;
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wire [ 2:0] fsm_q;
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rib2apb_formal_design u_design (
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.clk_i (clk_i),
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.rst_n_i (rst_n_i),
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.f_past_valid (f_past_valid),
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.rib_cmd_valid (rib_cmd_valid),
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.rib_cmd_addr (rib_cmd_addr),
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.rib_cmd_write (rib_cmd_write),
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.rib_cmd_len (rib_cmd_len),
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.rib_cmd_ready (rib_cmd_ready),
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.rib_w_valid (rib_w_valid),
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.rib_wdata (rib_wdata),
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.rib_wstrb (rib_wstrb),
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.rib_wlast (rib_wlast),
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.rib_w_ready (rib_w_ready),
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.rib_rsp_valid (rib_rsp_valid),
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.rib_rdata (rib_rdata),
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.rib_resp_err (rib_resp_err),
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.rib_resp_code (rib_resp_code),
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.rib_rsp_beat (rib_rsp_beat),
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.rib_rsp_last (rib_rsp_last),
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.rib_rsp_ready (rib_rsp_ready),
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.psel_comb (psel_comb),
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.psel_q (psel_q),
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.xfer_ready (xfer_ready),
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.xfer_error (xfer_error),
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.rsp_input_valid(rsp_input_valid),
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.rsp_input_ready(rsp_input_ready),
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.rsp_input_data (rsp_input_data),
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.fsm_q (fsm_q)
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);
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always @(posedge clk_i) begin
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if (f_past_valid && $past(rst_n_i && rib_cmd_valid && !rib_cmd_ready)) begin
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assume (rib_cmd_valid);
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assume (rib_cmd_addr == $past(rib_cmd_addr));
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assume (rib_cmd_write == $past(rib_cmd_write));
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assume (rib_cmd_len == $past(rib_cmd_len));
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end
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if (f_past_valid && $past(rst_n_i && rib_w_valid && !rib_w_ready)) begin
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assume (rib_w_valid);
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assume (rib_wdata == $past(rib_wdata));
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assume (rib_wstrb == $past(rib_wstrb));
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assume (rib_wlast == $past(rib_wlast));
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end
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if (rst_n_i) begin
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assert ($onehot0(psel_comb));
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if (f_past_valid && $past(rst_n_i && fsm_q == FSM_ENAB && !xfer_ready)) begin
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assert (fsm_q == FSM_ENAB);
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assert (psel_q == $past(psel_q));
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end
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if (fsm_q == FSM_ENAB && xfer_ready) begin
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assert (rsp_input_valid);
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assert (rsp_input_data[38:36] == 3'b100);
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assert (rsp_input_data[32] == xfer_error);
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assert (rsp_input_data[35:33] == (xfer_error ? RIB_RESP_SLVERR : RIB_RESP_OK));
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end
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if (fsm_q == FSM_ERR) begin
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assert (rsp_input_valid);
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assert (rsp_input_data[38:36] == 3'b100);
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assert (rsp_input_data[32]);
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end
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cover (fsm_q == FSM_ENAB && xfer_ready && rsp_input_ready);
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end
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end
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endmodule
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